IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Công bố khoa học tiêu biểu

* Dữ liệu chỉ mang tính chất tham khảo

Sắp xếp:  
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 9 - Trang 1088-1094 - 2002
V. Iyengar, K. Chakrabarty
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource conflicts, and limit power dissipation during test mode. In this paper, we present an integrated approach to several test scheduling problems. We first present a method to determine optimal schedules for reasonably sized ...... hiện toàn bộ
#System-on-a-chip #System testing #Optimal scheduling #Job shop scheduling #Automatic testing #Scheduling algorithm #Automation #Power dissipation #Heuristic algorithms #Polynomials
Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 32 Số 11 - Trang 1762-1775 - 2013
Panagiotis Sismanoglou, Dimitris Nikolos
On X-Variable Filling and Flipping for Capture-Power Reduction in Linear Decompressor-Based Test Compression Environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 31 Số 11 - Trang 1743-1753 - 2012
Xiao Liu, Qiang Xu
An efficient test vector compression scheme using selective huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 22 Số 6 - Trang 797-806 - 2003
Abhijit Jas, J. Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba
Techniques for minimizing power dissipation in scan and combinational circuits during test application
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 17 Số 12 - Trang 1325-1333 - 1998
V. Dabholkar, S. Chakravarty, Irith Pomeranz, S.M. Reddy
Embedded Deterministic Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 23 Số 5 - Trang 776-792 - 2004
Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
Variable-length input huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 22 Số 6 - Trang 783-796 - 2003
P.T. Gonciari, Bashir M. Al‐Hashimi, Nicola Nicolici
Low-power scan testing and test data compression for system-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 5 - Trang 597-604 - 2002
Anshuman Chandra, Krishnendu Chakrabarty
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 20 Số 3 - Trang 355-368 - 2001
Anshuman Chandra, Krishnendu Chakrabarty
A unified approach to reduce soc test data volume, scan power and testing time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 22 Số 3 - Trang 352-362 - 2003
Anshuman Chandra, Krishnendu Chakrabarty
Tổng số: 67   
  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7