IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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BDD minimization by scatter search
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 8 - Trang 974-979 - 2002
Reduced-ordered binary decision diagrams (BDDs) are a data structure for representation and manipulation of Boolean functions. The variable ordering largely influences the size of the BDD, varying from linear to exponential. In this paper, the authors study the BDD minimization problem based on scatter search optimization. Scatter search offers a reasonable compromise between quality (BDD reductio...... hiện toàn bộ
#Binary decision diagrams #Scattering #Boolean functions #Data structures #Logic design #Logic testing #Minimization #Benchmark testing #Genetic algorithms #Simulated annealing
An instruction-level energy model for embedded VLIW architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 9 - Trang 998-1010 - 2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power consumption information during either an instruction-level simulation or power-oriented scheduling at compile time. The analytical model takes into account several software-level parameters (such as instruction ordering,...... hiện toàn bộ
#VLIW #Energy consumption #Engines #Processor scheduling #Analytical models #Pipeline processing #Application software #Microarchitecture #Instruction sets #Digital signal processing
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 9 - Trang 1088-1094 - 2002
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource conflicts, and limit power dissipation during test mode. In this paper, we present an integrated approach to several test scheduling problems. We first present a method to determine optimal schedules for reasonably sized ...... hiện toàn bộ
#System-on-a-chip #System testing #Optimal scheduling #Job shop scheduling #Automatic testing #Scheduling algorithm #Automation #Power dissipation #Heuristic algorithms #Polynomials
Value-sensitive automatic code specialization for embedded software
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 9 - Trang 1051-1067 - 2002
The objective of this work is to create a framework for the optimization of embedded software. We present algorithms and a tool flow to reduce the computational effort of programs, using value profiling and partial evaluation. Such a reduction translates into both energy savings and average-case performance improvement, while preserving a tolerable increase of worst case performance and code size....... hiện toàn bộ
#Embedded software #Embedded system #Energy consumption #Application software #Costs #Clocks #Automatic control #Search engines #Consumer electronics #Multimedia systems
Algorithm level recomputing using allocation diversity: a register transfer level approach to time redundancy-based concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 9 - Trang 1077-1087 - 2002
In this paper, the authors propose an algorithm-level time redundancy-based concurrent error detection (CED) scheme against permanent and transient faults by exploiting the hardware allocation diversity at the register transfer level. Although the normal computation and the recomputation are carried out on the same data path, the operation-to-operator allocation for the normal computation is diffe...... hiện toàn bộ
#Redundancy #Fault detection #Circuit faults #Hardware #Electrical fault detection #Adders #Error correction #Registers #Very large scale integration #Logic
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 8 - Trang 889-903 - 2002
Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level parallelism inherent in many embedded media applications, while unlocking a variety of possible performance/cost tradeoffs. In this work, the authors propose a methodology to support early design space exploration of cluster...... hiện toàn bộ
#VLIW #Space exploration #Clocks #Algorithm design and analysis #Application specific processors #Registers #Computer architecture #Parallel processing #Time factors #Radio frequency
High-level energy macromodeling of embedded software
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 9 - Trang 1037-1050 - 2002
Presents an efficient and accurate high level software energy estimation methodology using the concept of characterization-based macromodeling. In characterization-based macromodeling, a function or subroutine is characterized using an accurate lower level energy model of the target processor to construct a macromodel that relates the energy consumed in the function under consideration to various ...... hiện toàn bộ
#Embedded software #Hardware #Computer architecture #Energy consumption #Power system modeling #Computer languages #Power dissipation #Software algorithms #Statistics
On the nonenumerative path delay fault simulation problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 9 - Trang 1095-1101 - 2002
The problem of determining the exact number of path delay faults that a given test set detects in a combinational circuit is shown to be intractable. This result further strengthens the importance of several recently proposed pessimistic heuristics as well as exact exponential algorithms for this nonenumerative problem. A polynomial time pessimistic algorithm which returns higher coverage than alg...... hiện toàn bộ
#Delay #Circuit faults #Circuit testing #Circuit simulation #Electrical fault detection #Fault detection #Polynomials #Combinational circuits #Physics computing #Robustness
Bridging fault modeling and simulation for deep submicron CMOS ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 8 - Trang 941-953 - 2002
Testing bridging faults in deep submicron CMOS digital ICs faces new problems because of pushing the technology limits. The growing dispersion of process parameters makes it hard to use conventional bridging fault models for high-quality testing. A new fault model is proposed to account for bridging faults in a way that is independent of electrical parameters and provides a significant coverage me...... hiện toàn bộ
#Semiconductor device modeling #Circuit faults #Integrated circuit testing #Logic testing #CMOS technology #Electrical fault detection #Fault detection #CMOS logic circuits #Performance evaluation #Logic devices
Design of reconfigurable composite microsystems based on hardware/software codesign principles
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Tập 21 Số 8 - Trang 987-995 - 2002
Composite microsystems that integrate mechanical and fluidic components with electronics are emerging as the next generation of system-on-a-chip. Custom microsystems are expensive, inflexible, and unsuitable for high-volume production. The authors address this problem by leveraging hardware/software codesign principles to design reconfigurable composite microsystems. They partition the system desi...... hiện toàn bộ
#Hardware #Robustness #System-on-a-chip #Design methodology #System performance #Response surface methodology #Application software #Microstructure #Design optimization #Production
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