A unified approach to reduce soc test data volume, scan power and testing time

Anshuman Chandra1, Krishnendu Chakrabarty1
1Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA

Tóm tắt

Từ khóa


Tài liệu tham khảo

berkelaar, 1999, lpsolve Vers 3 0

10.1109/VTS.2001.923416

10.1109/TCAD.2002.802256

huang, 2002, optimal core wrapper width selection and soc test scheduling based on 3-d bin packing algorithm, Proc Eur Test Workshop Dig Papers, 35

10.1109/ATS.2001.990293

10.1109/VTEST.1998.670873

10.1109/ICCAD.1998.144279

10.1049/el:20010981

10.1109/43.998630

10.1109/VTS.2001.923418

10.1145/378239.378388

10.1109/VTS.2002.1011118

10.1109/TEST.2001.966696

10.1109/12.364534

10.1109/DATE.2000.840866

10.1109/TEST.2000.894297

10.1109/TEST.2001.966687

10.1109/VTS.2001.923454

10.1109/VTEST.2000.843823

10.1109/43.875306

10.1109/54.953275

10.1109/TEST.2001.966672

10.1109/TCAD.2002.801102

10.1109/43.913754

10.1109/TEST.1998.743186

10.1109/TEST.1998.743187

10.1109/DELTA.2002.994661

10.1109/DATE.2002.998363

10.1109/FTCS.1999.781060

10.1109/TEST.2001.966671

10.1109/VTEST.1993.313316

10.1109/TEST.1999.805616

10.1109/TEST.2001.966685

10.1109/VTEST.1999.766696

10.1109/43.736572

10.1109/DAC.1997.597219

10.1109/VTEST.2000.843824

10.1109/43.771184