Techniques for minimizing power dissipation in scan and combinational circuits during test application

abramovici, 1990, Digital Systems Testing and Testable Design

10.1109/ICCAD.1993.580166

weste, 1992, Principles of CMOS VLSI Design A Systems Perspective

marculescu, 1994, logic level power estimation considering spatiotemporal correlations, Proc ACM/IEEE Int Conf Computer-Aided Design, 294

10.1109/43.45875

stamoulis, 1993, improved techniques for probabilistic simulation including signal correlation effects, 30th ACM/IEEE Design Automation Conference, 379, 10.1145/157485.164939

10.1109/ICCAD.1993.580061

dabholkar, 1996, Optimization problems in low-power and stress testing

10.1287/opre.37.6.865

ha, 1994, ATALANTA An ATPG Tool

tsui, 1993, technology decomposition and mapping targeting low power dissipation, 30th ACM/IEEE Design Automation Conference, 68, 10.1145/157485.164577

10.1109/ICCD.1992.276316

10.1109/EURDAC.1993.410619

tiwari, 1993, technology mapping for low power, 30th ACM/IEEE Design Automation Conference, 74, 10.1145/157485.164581

10.1109/ICVD.1994.282700

10.1109/MCMC.1992.201438

10.1109/DAC.1992.227826

10.1109/TEST.1994.527956

10.1109/ICCAD.1992.279338

10.1109/43.238040

lawler, 1976, Combinatorial Optimization Networks and Matroids

lawler, 1985, The Traveling Salesman Problem

brglez, 1985, a neutral netlist of 10 combinational benchmark circuits and a target translator in fortran, Proc ACM/IEEE Int Symp Circuits and Systems

cormen, 1991, Introduction to Algorithms

10.1109/43.108614