IEEE Electron Device Letters

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate Fowler-Nordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si/SiO/sub 2/ interface during the FG dry-etching, prior to the backend processes such as metal- or via-etch.

High Q-values of spiral inductors at frequency around 5/spl sim/6 GHz have been achieved with a multilayer spiral (MLS) structure on a high loss silicon substrate. Compared to a one-layer spiral (OLS) inductor, the Q-value of a 4-nH inductor has been improved by about 80% at 5.65 GHz. The impact of the structure on Q-value and resonant frequency has been analyzed, which shows that an optimal height for the via of MLS inductors should be considered when inductors are designed. The fabrication process is compatible with Cu/SiO/sub 2/ interconnect technology.

We have studied the Ni and Co germano-silicide on Si/sub 0.3/Ge/sub 0.7//Si. The Ni germano-silicide shows a low sheet resistance of 4-6 /spl Omega///spl square/on both P/sup +/N and N/sup +/P junctions, which is much smaller than Co germano-silicide. In addition, small junction leakage currents of 3/spl times/10/sup -8/ A/cm/sup 2/ and 2/spl times/10/sup -7/ A/cm/sup 2/ are obtained for Ni germano-silicide on P/sup +/N and N/sup +/P junctions, respectively. The good germano-silicide integrity is due to the relatively uniform thickness as observed by cross-sectional TEM.

For the first time, we have successfully demonstrated the feasibility of integrating a high-permittivity (/spl kappa/) gate dielectric material zirconium oxide into the MOS capacitors fabricated on pure germanium substrates. The entire fabrication process was essentially performed at room temperature with the exception of a 410/spl deg/C forming gas anneal. After processing steps intended to remove the germanium native oxide interlayer between the zirconium oxide dielectric and germanium substrate, an excellent capacitance-based equivalent SiO/sub 2/ thickness (EOT) on the order of 5-8 /spl Aring/ and capacitance-voltage (C-V) characteristics with hysteresis of 16 mV have been achieved. Additionally, excellent device yield and uniformity were possible using this low thermal budget process.

The low temperature (100/spl deg/C) deposition of Sc2O3 or MgO layers is found to significantly increase the output power of AlGaN/GaN HEMTs. At 4 GHz, there was a better than 3 dB increase in output power of 0.5×100 μm2 HEMTs for both types of oxide passivation layers. Both Sc2O3 and MgO produced larger output power increases at 4 GHz than conventional plasma-enhanced chemical vapor deposited (PECVD) SiN/sub x/ passivation which typically showed /spl les/2 dB increase on the same types of devices. The HEMT gain also in general remained linear over a wider input power range with the Sc2O3 or MgO passivation. These films appear promising for reducing the effects of surface states on the DC and RF performance of AlGaN/GaN HEMTs.

A novel GaN/AlGaN p-channel inverted heterostructure junction field-effect transistor (HJFET) with a n/sup +/-type gate is proposed and demonstrated. A new superlattice aided strain compensation techniques was used for fabricating high quality GaN/AlGaN p-n junction. The p-channel HJFET gate leakage current was below 10 nA, and the threshold voltage was 8 V, which is close to that of typical n-channel HFETs. This new HJFET device opens up a way for fabricating nitride based complimentary integrated circuits.

We propose and demonstrate an integrated power MOSFET structure where a fast-switching antiparallel rectifier with improved reverse recovery is integrated within the conventional DMOSFET structure. In this device, the source metal electrode of the DMOSFET is extended to the n-drift region, and a thin p-layer is implanted under the metal forming a junction diode antiparallel to the DMOSFET. Analysis of the experimental switching performance of the integral diode in 500-V integrated power DMOSFET/antiparallel rectifier devices indicates at least 30% decrease in peak reverse current and minority carrier stored charge at 100/spl deg/C.