IEEE Electron Device Letters

Một mô hình giữ điện tử cho điện tích cục bộ, bị bẫy trong lớp điện môi ONO xếp chồng, được giới thiệu sử dụng thiết bị bộ nhớ chỉ đọc nitrua (NROM). Sự giảm ngưỡng điện áp (mất giữ) quan sát được của một ô đã được lập trình được giải thích theo việc phân phối lại điện tích theo phương ngang trong lớp nitrua. Giả sử cơ chế phát xạ nhiệt, các mức năng lượng của các bẫy điện tử đã được trích xuất và phát hiện phân bố liên tục trong khoảng cách băng nitrua, với giá trị trung vị khoảng /spl sim/2.12 eV dưới dải dẫn. Sử dụng các phát hiện này, mô hình cho phép dự đoán mất giữ trên phạm vi nhiệt độ rộng, từ 140/spl deg/C-300/spl deg/C, trong thời gian dài, lên đến 10/sup 7/ giây, mức mất giữ lớn, khoảng /spl sim/90%, và các khoảng lập trình từ 1.9-3.3 V. Dựa trên công việc này, mất giữ tương đối sau mười năm ở 140/spl deg/C của một ô NROM dự kiến sẽ là 14% (V/sub DS/=0.1 V) và mất sản phẩm tương đương chưa chu kỳ được dự kiến là 8%.

Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga2O3 gate oxide, an undoped Al/sub 0.75/Ga/sub 0.25/As spacer layer, and undoped In/sub 0.2/Ga/sub 0.8/As as channel layer. The p-channel devices with a gate length of 0.6 μm exhibit a maximum DC transconductance g/sub m/ of 51 mS/mm which is an improvement of more than two orders of magnitude over previously reported results. With the demonstration of a complete process flow and 66% of theoretical performance, GaAs MOS technology has moved into the realm of reality.

In this work, a quantitative analysis is applied to resolve the newly reported polarity-dependent charge-to-breakdown (Q/sub BD/) data from thick oxides of 6.8 nm down to ultrathin oxides of 1.9 nm. Three independent sets of Q/sub BD/ data, i.e., n/sup +/poly/NFET stressed under inversion and accumulation, and p/sup +/ poly/PFET under accumulation are carefully investigated. The Q/sub BD/ degradation observed for p-type anodes, either poly-Si or Si-substrate, can be nicely understood with the framework of maximum energy released by injected electrons. Thus, this work provides a universal and quantitative account for a variety of experimental observations in the time-to-breakdown (T/sub BD/) and Q/sub BD/ polarity-dependence of oxide breakdown.

We demonstrate a novel RF switch based on a multifinger AlGaN/GaN MOSHFET. Record high saturation current and breakdown voltage, extremely low gate leakage current and low gate capacitance of the III-N MOSHFETs make them excellent active elements for RF switching. Using a single element test circuit with 1-mm wide multifinger MOSHFET we achieved 0.27 dB insertion loss and more than 40 dB isolation. These parameters can be further improved by impedance matching and by using submicron gate devices. The maximum switching power extrapolated from the results for 1A/mm 100 μm wide device exceeds 40 W for a 1-mm wide 2-A/mm MOSHFET.

An improved two-frequency method of capacitance measurement for the high-k gate dielectrics is proposed. The equivalent circuit model of the MOS capacitor including the four parameters of intrinsic capacitance, loss tangent, parasitic series inductance, and series resistance is developed. These parameters can be extracted by independently measuring the capacitor at two different frequencies. This technique is demonstrated for high-k SrTiO/sub 3/ gate dielectrics and the results show that the calibrated capacitances are invariant over a wide range of frequency. In addition, the extracted loss tangent, inductance and resistance are independent on gate voltage and frequency. The effect of series resistance on the frequency dispersion of the capacitance can be also explained by this model. These results indicate that this modified technique can be incorporated in the routine capacitance-voltage (C-V) measurement procedure providing the physically meaningful data for the high-k gate dielectrics.

A novel hexagonal binary-decision-diagram (BDD) quantum logic circuit approach for III-V quantum large scale integrated circuits is proposed and its basic feasibility is demonstrated. In this approach, a III-V hexagonal nanowire network is controlled by Schottky wrap gates (WPGs) to implement BDD logic architecture by path switching. A novel single electron BDD OR logic circuit is successfully fabricated on a GaAs nanowire hexagon and correct circuit operation has been confirmed from 1.5 K to 120 K, showing that the WPG BDD circuit can operate over a wide temperature range by trading off between the power-delay product and the operation temperature.

This letter reports on the room temperature operation of a conventional SiGe bipolar ECL ring oscillator with a minimum stage delay of 4.2 ps for /spl sim/250 mV single ended voltage swing. To our knowledge, this is the lowest reported delay for a gate fabricated using transistor devices. The circuit uses 0.12 × 2 μm2 emitter size SiGe n-p-n transistors with a room temperature fT of 207 GHz and fmax (unilateral gain extrapolation) of 285 GHz. The ring oscillator was studied as a function of various device and circuit parameters and it was found that minimum delay is more dependent on the parasitic resistance and capacitance in the n-p-n device than on pure transit time across the device.

Metal-insulator-metal (MIM) capacitors with a 56 nm thick HfO/sub 2/ high-/spl kappa/ dielectric film have been fabricated and demonstrated for the first of time with a low thermal budget (/spl sim/200/spl deg/C). Voltage linearity, temperature coefficients of capacitance, and electrical properties are all characterized. The results show that the HfO/sub 2/ MIM capacitor can provide a higher capacitance density than Si/sub 3/N/sub 4/ MIM capacitor while still maintaining comparable voltage and temperature coefficients of capacitance. In addition, a low leakage current of 2/spl times/10/sup -9/ A/cm/sup 2/ at 3 V is achieved. All of these make the HfO/sub 2/ MIM capacitor to be very suitable for use in silicon RF and mixed signal IC applications.

Using a relatively large size MOSFET (W/L= 15/15 μm), we investigated the degradation of MOSFET characteristics due to localized copper contamination. In order to contaminate a part of the active region of MOSFET, silicon nitride (Si3N4) over the active region, which is known to be a protective film against copper, was etched by reactive ion etching (RIE). As the area of localized copper contamination is about 3-4 μm or above, apart from the edge of the gate electrode, no degradation was observed after thermal treatment at 450/spl deg/C for 2 h in N2 ambient, based on the result of the increase in interface trap density (/spl Delta/D/sub it/).

For the first time we describe a positive application of electromigration, as an electrically programmable fuse device (eFUSE). Upon programming, eFUSE's show a large increase in resistance that enable easy sensing. The transient device characteristics show that the eFUSE stays in a low resistance state during programming due to the local heating of the fuse link. The programming is enhanced by a device design that uses a large cathode which increases the temperature gradient and minimizes the effect of microstructural variations.