Optimization of series resistance in sub-0.2 /spl mu/m SOI MOSFET's

IEEE Electron Device Letters - Tập 15 Số 9 - Trang 363-365 - 1994
L.T. Su1, M. Sherony1, Hang Hu1, Jaewoo Chung1, Dimitris Antoniadis1
1Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA

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