Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel

IEEE Electron Device Letters - Tập 34 Số 7 - Trang 897-899 - 2013
Hung-Bin Chen1, Chun-Yen Chang1, Nan-Heng Lu2, Jui-Sheng Wu1, Ming-Hung Han1, Ya-Chi Cheng2, Yung‐Chun Wu2
1Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
2Department of Engineering and System Science, National Tsing Hua University, Hsinchu, Taiwan

Tóm tắt

Từ khóa


Tài liệu tham khảo

10.1109/IEDM.2006.346840

trevisoli, 2011, Threshold voltage in junctionless nanowire transistors, Semicond Sci Technol, 26, 105009, 10.1088/0268-1242/26/10/105009

10.1063/1.2894590

10.1116/1.3499648

cheng, 2012, Sub-10-nm nano-sheet channel of junctionless poly-Si TFT with oxidation thinning method, Proc Solid State Devices Mater Conf, 805

10.1109/LED.2011.2107498

10.1038/nature10676

10.1109/VLSIT.2010.5556191

10.1109/LED.2011.2171914

colinge, 2011, Junctionless Transistors Physics and Properties Semiconductor-On-Insulator Materials for Nanoelectronics Applications, 187, 10.1007/978-3-642-15868-1_10

10.1109/IRPS.2011.5784464

10.1038/nnano.2010.15

10.1109/TED.2004.827382

10.1063/1.3079411

Thông tin
Thông tin xuất bản

IEEE Electron Device Letters

Tập 34 Số 7

897-899

Thông tin tác giả