Analog Integrated Circuits and Signal Processing

This article contributes a new configuration of the current mode (CM) sinusoidal oscillator employing a single voltage differencing transconductance amplifier (VDTA), as an active building block, and all grounded passive elements. This fully electronically tunable circuit offers independent control of its design parameters i.e., oscillation condition (OC) and oscillation frequency (OF). To validate the design concept, along with the regular mathematics, simulations have been performed using PSPICE software. Experimental results have been obtained by the commercially available IC i.e., LM13700, to validate the theoretical expectations.

A detection and compensation technique for LO phase mismatches is presented to reduce noise in the mixer. Based on theoretical analysis and simulation, this work shows that the LO phase mismatch degrades the noise figure, gain, and linearity of the mixer. To compensate the LO phase mismatch, a new concept of the mixer is proposed, and its prototype is fabricated in 0.18-μm CMOS technology. In addition, a current bleeding mixer, which is known for low flicker noise topology, is also fabricated for comparative purposes. From the measured results, the proposed mixer reduces the flicker noise corner frequency by almost half when it is compared to the current bleeding mixer. Moreover, the proposed mixer improves gain and linearity without additional power consumption.

A charge pump is a widely used circuit in modern PLLs. In order to reduce phase offset, and decrease spurs tones in the PLL output signals, the charge pump current mismatch has to be minimized. In this paper, a charge pump circuit with low current mismatch characteristic that was designed with a standard 0.18 $$\upmu $$ m CMOS technology. A Mentor Graphics environment using Eldo program was used to carry out the schematic, layout, and post-layout simulations. Under 1.8 V DC supply voltage, and 100 $$\upmu $$ A output current, the circuit consumes only 0.56 mW in fully differential mode, and 0.38 mW for a single ended configuration. Using the same bias current for UP, and DN signals, and three wide-swing current mirrors a 0.32 % current mismatch with a 0.3–1.5 V wide output voltage range was achieved. The circuit can be widely used in either single-ended or fully differential phase locked loop structures.

This paper presents an integration-leakage calibration technique for the switched-capacitor integrators in a delta-sigma modulator (DSM). Integrators realized with low-gain opamps are lossy. A DSM that uses lossy integrators exhibits a degraded signal-to-quantization-noise ratio. To calibrate an integrator, its integration leakage is detected in the digital domain, and the leakage compensation is applied to the same integrator in the analog domain. The proposed scheme can calibrate all integrators in a discrete-time DSM of any form. It can be proceed in the background without interrupting the normal DSM operation. The design considerations for the proposed calibration scheme are discussed. Design cases of a 1st-order, a 2nd-order, and a 3rd-order DSM are demonstrated and simulated.

This paper presents a 7.5 GS/s, 4.5 bit flash analog-to-digital converter (ADC) for high-speed backplane communication. A two-stage track-and-hold (T/H) structure enables high input bandwidth and low power consumption at the same time. A sampling clock duty cycle control technique, which allocates more tracking time to the bandwidth-limited second T/H stage, facilitates high sampling rates. A digital offset correction scheme compensates both random and systematic offsets due to process variation and T/H amplifier gain nonlinearity, simultaneously. Two test-chip prototypes were fabricated in a 65 nm CMOS process. Experimental results of a standalone ADC chip demonstrate 3.8 effective number of bits (ENOB) at 7.5 GS/s. The figure-of-merit (FOM) of the standalone ADC is 0.49 pJ/conversion-step. The second test chip combines two ADCs together in order to demonstrate a time-interleaved ADC (TI-ADC) for use in high-speed backplane receivers. The TI-ADC operates at 10.24 GS/s while achieving 3.5 ENOB and 0.65 pJ/conversion-step FOM.

Digital-to-analog converts utilizing neuron MOS-transistors were designed. Different DACs were implemented and characterized in order to compare various topologies. Criteria to select structures were low power, fast performance and minimal silicon area. A basic 8-bit version is implemented with only one neuron MOS-transistor and eight capacitors. The silicon area of this D/A converter is only 0.04 mm2 and the power consumption is 8.4 mW with conversion speed of 200 MS/s. An enhanced 8 and 10 bit versions utilizing neuron PMOS transistor and some extra circuitry are also proposed and tested. The silicon area of the enhanced 10 bit circuit is only 0.03mm2 while the performance is as good as in the case of the basic version. The measured differential nonlinearity is 0.38 LSB and integral nonlinearity is 0.55 LSB for the enhanced 10 bit structure.

A CMOS inductorless image-reject filter based on active RLC circuitry is discussed and designed with the emphasis on low-noise, low-power, and gigahertz-range circuits. Two $$Q$$ -enhancement techniques are utilized to circumvent the low $$Q$$ characteristics inherent in the simple feedback circuit. The frequency tuning is almost independent of $$Q$$ tuning, facilitating the design of the automatic tuning circuitry. The stability and the tuning scheme of the filter are also discussed. Simulations using 0.6 μm CMOS technology demonstrate the feasibility of the tunable image-reject filter for GSM wireless applications. Simulation results show 4.75 dB voltage gain, 9.5 dB noise figure, and −20 dBm IIP3 at a passband centered at 947 MHz. The image signal suppression is 60 dB at 1089 MHz and the power consumption is 27 mW.

Effective parameter extraction is a crucial step in accurate simulation of microelectronic circuits and systems. A parameter extraction program, which is based on a global optimization algorithm, uses a single objective function that minimizes the drain current error between the predicted and measured data. Parameter sets extracted on this basis are adequate for the purpose of digital circuit simulation, but fall short of simulation requirements for analog circuits. The use of a multiple-objective function is proposed, which simultaneously optimizes several critical electrical quantities including the drain current, output conductance, and transconductance. Experimental results with the multiple-objective function are presented, to show the improvement in extracted parameters. The recently developed BSIM_plus MOS transistor model for sub-half-micron integrated circuits uses a compact set of parameters, which greatly enhances the ability to accurately extract parameter values. This model was implemented into the parameter extraction program and some extraction results are presented. The parameter space has several local minima within which a gradient descent method may be trapped. Simulated annealing techniques can be applied to find near-optimal solutions of problems containing multiple local minima in their solution spaces. Experimental results showing the optimization of drain current error using simulation annealing techniques are presented.