Analog Integrated Circuits and Signal Processing

In the paper, a novel four-wing chaotic system was constructed based on a Lorenz-like system. The novel chaotic system had rich dynamic characteristics such as four-wing attractors, widely chaotic regions, high SE complexity, and multiple transient transitions. Meanwhile, the weak chaotic attractors with single-wing and double-wing can be observed through changing the system parameters. NIST tests showed that the system had high complexity, which will have a good application value in secure communication and cryptography. In addition, a corresponding hardware analog circuit was designed based on the novel chaotic system with operational amplifiers and multipliers. The experimental results were agreed with the theoretical analysis, which verified that the novel chaotic system was practical feasibility.

This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 μm CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. Maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption.

This paper presents a new modelling method for MEMS components based on the Cosserat theory. By constructing Cosserat rod elements, generating symbolic code and developing numeric code in VHDL-AMS for selected demonstrators, we are able to effectively simulate and predict the essential linear and nonlinear behaviour in estimating system performance and guiding the reliability verification process. The simplicity of the Cosserat approach follows from the possibility to formulate interconnected slender components in terms of a network of quasi-rigid bodies (Cosserat elements). This modularization fits well into the behavioural modelling where a relatively low degree of freedom is needed to capture salient features of the system. Furthermore, the manner in which Cosserat elements and their interactions are formulated makes this method ideally suited for nonlinear dynamic simulations in the presence of large deflections.

Two integrated stereo fully differential filterless class-D amplifiers are presented in this paper. The object is to develop a modulation of a class-D audio amplifier with high power efficiency in this paper. The traditional H-bridge class-D audio amplifier has a shortcoming of large signal distortion which is worse than realized. However, the proposed circuit improves the drawback and provides high power efficiency at the same time. The circuit implements a modified scheme of pulse-width modulation. In this paper, we presented two class-D amplifiers, compared their differences and explained why the efficiency and distortion performance can be modified. The increase in total harmonic distortion (THD) is due to non-linearity in the triangle wave. To overcome this problem, a negative feedback from the output of the switching power stage is adopted to reduce the THD. When a 0.7-VPP and 1 kHz sine wave is used as an input signal, the minimum THD is 0.029 % and the maximum power efficiency is 83 %. The fully differential class-D audio amplifier is implemented with a TSMC 0.35-μm 2P4M CMOS process, and the chip area is 2.57 × 2.57 mm2 (with PADs).

Software-Defined Radio (SDR) provides a flexible platform that facilitates radio resource management and enables new technologies and applications. Unfortunately, their reliance on software implementations makes them vulnerable to malicious software attacks that could impact their spectral emissions and disclose sensitive information. It is of critical importance for the widespread deployment of SDR to develop technologies that enable effective integrity assessment of communications platforms and timely detection of malicious intrusions. We provide further evidence of the feasibility of a novel approach called Power Fingerprinting (PFP) that enables an effective mechanism to perform integrity assessment of SDR. PFP relies on an external monitor that captures fine-grained measurements of the processor’s power consumption and compares them against stored signatures from trusted software by applying pattern recognition and signal detection techniques. Because it is implemented by an external monitor, PFP causes minimal disruption on the target system and also provides the necessary isolation to protect against malicious attacks to the monitor itself. Fine-granularity measurements deliver improved visibility into the execution status and make the PFP monitor difficult to evade, while the reliance on anomaly detection from trusted references makes it effective against zero-day attacks. We present the results of different feasibility experiments that support the applicability of PFP to SDR integrity assessment. In the first experiment, a PFP monitor is able to effectively detect the execution of a tampered routine that misconfigures the operational mode of a PICDEM Z radio platform, affecting the resulting spectral emission. In a second experiment, our monitor effectively identifies when a transmission routine is modified, affecting encryption settings. We also present an approach to improve the performance of PFP by characterizing the way a specific platform consumes power. This platform characterization, which can be done using principal component analysis or linear discriminant analysis, allows a PFP monitor to work only on the features that carry the most information. As a result, the PFP monitor is able to detect execution deviations resulting from a difference of a single bit transition, the smallest possible disruption.

A novel small-sized voltage mode noise canceling circuit is introduced in order to remove the dv/dt noise in the ultra-high-voltage MOS gate drive IC more efficiently, accurately and steadily. The dv/dt noise is removed completely by the mutual controlling of the high-side voltage signal, which improves the incapability of the full removal of dv/dt noise by conventional noise remove circuit due to the mismatch in the high-side circuit. In addition, no additional circuit is introduced to the noise canceling circuit. Fabricated in 700 V 0.5 μm BCD with simulation tool HspiceD, the circuit shows good performances of a quiescent current less than 50 μA, and a full removal of 70 V/ns dv/dt noise by the noise elimination function block. Moreover, a mismatch rate ranging within ±100 % can also be fully eliminated, thus ensuring the stability and reliability of the ultra-high-voltage gate driver’s performance.

Silicon sensor systems are based on capability of siliconto serve as a basic material for monolithic cointegration ofsensors and electronics. Implementation of this cointegration,its advantages and benefits, and examples of silicon sensor systemsform the central part of this contribution.

This paper presents a wideband low power balun LNA with double noise canceling techniques and symmetric outputs. First, the CS amplifier in parallel with the CG stage cancels the noise and distortion of the CG amplifier. Second, an auxiliary amplifier (Aux) is employed in the CS stage to reduces the noise of the CS stage and avoids traditional up scaling of the CS stage. Moreover, the employed Aux stage reduces the output impedance and allows CG and CS stages to drive equal loads. The modified CS stage overcomes the disadvantages of high power consumption and weak output balance in conventional balun LNAs and improves IIP2. Besides, a feedback loop is utilized around the CG amplifier to match the input in a wide frequency band utilizing a low power CG stage. Lower transconductance in the CS stage beside the current reused technique in the CG stage significantly reduces power consumption. The post-layout simulation of the proposed LNA in 180 nm RF CMOS process shows a maximum voltage gain of 20.2 dB with − 3 dB bandwidth of 0.4–2.8 GHz. The minimum NF is 2.65 dB with input matching better than − 12 dB in BW. The third input intercept point (IIP3) is − 0.008 dBm. The consuming power is 4.5 mW from 1.5 V DC supply and the chip area is only 0.038 mm2.

A novel current-mode (CM) single-input and three-output (SITO) universal filter using two second generation current controlled conveyors (CCCIIs), one current follower (CF) and two capacitors is presented. The circuit is fully programmable and implements all the five generic filtering functions. The lowpass (LP), bandpass (BP), and highpass (HP) functions can be realized simultaneously while Notch (BS) and allpass (AP) responses can be implemented simply by connecting the appropriate node currents without requiring additional elements. The availability of currents at high impedances, facilitate cascadibility feature. The filter performance factors ω0 and ω0/Q are electronically tunable through separate bias currents of the CCCIIs. SPICE simulation results are included to confirm the workability of the proposed circuit.

A 4 GHz ΔΣ fractional-N frequency synthesizer for wireless communications applications is implemented in a 0.35 μm BiCMOS process. The synthesizer achieves a close-in phase noise of −66 dBc/Hz. The key building blocks are an ECL multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation, a digital third-order MASH ΔΣ-modulator that controls the modulus of the prescaler, a very linear phase detector that enables the synthesizer to achieve a low close-in phase noise, and a chargepump providing a constant output current over a large output voltage range. The power dissipation of the synthesizer chip is 27.7 mW from a 2.7 V supply.