Analog Integrated Circuits and Signal Processing

The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f in = 1.83, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 μm CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR ≥ 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.

A new technique for CMOS inverter-based tunable transconductors is proposed in this paper. The proposed technique employs the master–slave approach and offers large transconductance tuning range using a control current. The transconductor was designed using triple-well 0.13 μm CMOS process under the ultra low supply voltage of 0.5 V. The circuit features 37 dB open loop gain, CMRR = 31 dB at each output node, PSRR = 90 dB and GBW = 530 MHz for 120 μA current consumption.

The clustering of spatio-temporal patterns are essential for many applications. Established from the biological analogy of the cortex, the parametrically coupled logistic map network (PCLMN) provides a viable solution to the clustering problem. To engineer for a single-chip spatio-temporal pattern clustering system, the highly modular PCLMN is designed in analog circuit. In this paper, the 0.6 μm 5 V CMOS design of the processing element is presented. The analog design employs self-calibration techniques to improve the accuracy and robustness of the nonlinear circuits. A fabricated element covers a die area of 0.55 mm2, and consumes 240 mW power at 5 V supply. After calibration, simulation and testing results show that the element fulfills the system-level requirement of the Cort-X model for driving signals up to 1 MHz.

Noise Efficiency Factor (NEF) is the most employed figure of merit to compare different low-noise biomedical signal amplifiers, taking into account current consumption, noise, or bandwidth trade-offs. A small NEF means a more efficient amplifier, and was assumed to be always NEF > 1 (an ideally efficient single BJT amplifier). In this work current-reuse technique will be utilized to exceed this limit in a very efficient CMOS amplifier. A micro-power, ultra-low-noise amplifier, aimed at electro-neuro-graph signal recording in a specific single-channel implantable medical device, is presented. The circuit is powered with a standard medical grade 3.6 V(nom) secondary battery. The amplifier input stage stacks twelve differential pairs to maximize current-reuse. The differential pair stacking technique is very efficient: allows most of the energy to be dissipated in the input transistors that amplify and not in mirror or bias transistors, and allows also the input transistors to operate with a reduced VDS just above saturation. The amplifier was implemented in a 0.6 μm technology, it has a total gain of almost 80 dB, with a 4 kHz bandwidth. The measured input referred noise is 4.5 nV/Hz1/2@1 kHz, and 330 nVrms in the band of interest, with a total current consumption of only 16.5 μA from the battery (including all the 4 stages and the auxiliary circuits). The measured NEF is only 0.84, below the classic NEF = 1 limit.

Circuits which achieve precise gains without the use of negative feedback are of interest because of their simplicity and potential for achieving large bandwidths. A circuit architecture based upon precision current mirrors for producing fixed gains without the use of feedback has been reported in the literature and implemented on a BiCMOS process [1]. This paper provides further analysis of this approach and applies it to a new bipolar amplifier, intended for such applications as real-time active filter synthesis.

A wideband current amplifier with DC-offset cancellation utilizing chopper modulation is proposed. Combining series–series feedback with backgate driven choppers, a wideband current amplifier with DC-offset cancellation is realized. As consumed a power of 1.495 mW under a supply voltage of 1.8 V, measured bandwidth of the current amplifier is 120 MHz, which leads the current amplifier can be adopted to compose the analog baseband of a wideband direct-conversion receiver with bandwidth of 240 MHz (twice of the baseband bandwidth). Measured current gain of the current amplifier is 15 dB. Measured output DC-offset without and with DC-offset cancellation are − 70.8 dBV and − 91 dBV, respectively. Thus, DC-offset reduction of 20 dB is achieved.

Power amplifier (PA) plays a key role in transceivers for mobile communication systems and the improvement of the linearity of the PA becomes an objective of first importance. This paper proposes a novel linearization method for PA based on the Legendre wavelet possessing rich properties, so as to this technique combines the advantages of piecewise linear functions and orthogonal polynomials for pre-distortion linearization. Pre-distorter (PD) has been identified and power spectrum also has been compared based on the data of the PA characteristics for WCDMA and OFDM signals, respectively. The computational results demonstrate that a quite significant improvement in linearity is achieved and the PD is stable and effective. The most attractive aspects of the presented method is that the Legendre wavelet bases can approximate static nonlinearity of the PA with different level of resolution and lower order piecewise polynomials than that of other polynomials.