GigaHertz MUX-DEMUX Chip with HF BIST

Analog Integrated Circuits and Signal Processing - Tập 12 - Trang 29-48 - 1997
Lars Hellberg1, Owe Thessén1, Hannu Tenhunen1, José-Maria Gobbi2
1Electronic Systems Design Laboratory (ESDlab), KTH-Electrum, Royal Institute of Technology, Kista, Sweden
2Ericsson Components AB, MERC, Kista, Sweden

Tóm tắt

Full functional test at speed, in-situ is an ideal choice for use for detection of errors in circuit behaviour for high speed broadband communication circuits and to avoid test set-up disturbances on high frequency signals. This article presents a novel technique to solve the high frequency test of Gbit/s data rate Time-Division Multiplexer/Demultiplexer circuits. This in-situ test technique is based on conventional pseudo-random sequence generation and signature analysis. By linear feedback interconnect and reusable architecture the multiplexer/demultiplexer circuits can operate as generator/analyser with minimal degeneration of bit shift rate. Circuit simulation showed that the system operates correctly with a clock frequency up to 3 GHz in a silicon bipolar technology with a current gain cut-off frequency f T = 15 GHz.

Tài liệu tham khảo

L. Ridell Virtanen, C. G. Thisell, I. Svedin, and J. M. Gobbi, “Testing Full Functionality of 3 Gbit/s 16:1 BiCMOS MUX at Speed On Wafer.” The European Design and Test Conference, Paris, France, 1996. Y. Zorian, “Tutorial on Design for Test of MCMs.” The European Design and Test Conference, Paris, France, 1995. T. Lazraq, P-O. Bergstedt, M. Mokhtari, and H. Tenhunen, “ATM Switch Core.” Royal Institute of Technology, KTH-Electrum, ESDlab, Kista, Sweden. T. Lazraq, “Design Techniques and Structures for ATM Switches.” Thesis for the degree of Doctor of Technology, KTH-Electrum, Stockholm, Nov. 15, 1995. I. Andersson, B. Rudberg, T. Lewin, M. Reed, S. Planer, and S. Sundaram, “Silicon Bipolar Chipset for SONET/SDH 10 Gb/s Fiber-Optic Communication Links.” IEEE Journal of Solid-State Circuits, 30(3), 1995. H. Rein, “Multi-Gigabit-Per-Second Silicon Bipolar IC's for Future Optical-Fiber Transmission Systems.” IEEE Journal of Solid-State Circuits, 23(3), 1988. R. David and P. Thévenod-Fosse, “Random Testing of Integrated Circuits.” IEEE Trans. on Instrumentation and Measurement, IM-30(1), 1981. T. W. Williams, VLSI Testing. North Holland, 1986. M. Mokhtari, T. Juhola, G. Schuppener, F. Sellberg, and H. Tenhunen, “Influence of Interconnect Parasitics on High Speed MS1 (V)LS1 Circuits at Gb/s Data-Rates.” Proceedings of the 13th Norchip Conference, Copenhagen, Denmark, 1995. J. M. Gobbi, T. Johansson, and L. R. Virtanen, “Underground capacitors. Very efficient decoupling for High Performance UHF signal processing ICs.” Proceedings of The European Design and Test Conference, Paris, France, 1994. H. M. Rein, “A 4:1 Time-Division Multiplexer IC for Bit Rates up to 6 Gbit/s Based on a Standard Bipolar Technology.” IEEE Journal of Solid-State Circuits, sc-21(5), 1986. P. H. Bardell, W. McAnney, and J. Savir, Built-In Test for VLSI: Pseudo-random Techniques. John Wiley & Sons: New York, 1987. E. J. McCluskey, Logic Design Principles, With Emphasis on Testable Semicustom Circuits. Prentice-Hall, 1986. K. J. Negus, “Multi-Gbits/s Silicon Bipolar Multiplexer and Demultiplexer with interleaved Architectures.” IEEE Bipolar Circuits and Technology Meeting 2.2, 1991. T. Nakamura and H. Nishizawa, “Recent Progress in Bipolar Transistor Technology.” IEEE Trans. on Electron Devices. 42(3), 1995. Z. Lao, U. Langmann, J. Albers, E. Schlag, and D. Clawin, “A 12 Gb/s Si Bipolar 4:1-Multiplexer IC for SDH Systems.” IEEE Journal of Solid-State Circuits, 30(2), 1995.