A small area 8 bits 50 MHz CMOS DAC for Bluetooth transmitter
Tóm tắt
This paper presents a small-area CMOS current-steering segmented digital-to-analog converter (DAC) design intended for RF transmitters in 2.45 GHz Bluetooth applications. The current-source design strategy is based on an iterative scheme whose variables are adjusted in a simple way, minimizing the area and the power consumption, and meeting the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy to attain a small-area current-steering DAC are included. The DAC was designed and implemented in 0.35 μm CMOS technology, requiring an active area of just 200 μm × 200 μm. Experimental results, with a full-scale output current of 700 μA and a 3.3 V power supply, showed a spurious-free dynamic range of 58 dB for a 1 MHz output sine wave and sampling frequency of 50 MHz, with differential and integral nonlinearity of 0.3 and 0.37 LSB, respectively.
Tài liệu tham khảo
Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design (2nd ed.). USA: Oxford University Press.
Balestrieri, E., Moisa, S., & Rapuano, S. (2005). DAC static parameter specifications—Some critical notes. In Proc. of 14th IMEKO International Symposium on New Technologies in Measurement and Instrumentation and 10th Workshop on ADC Modelling and Testing, Gdynia, Poland 1, pp. 81–86.
Gostner, T. (2000). The design of current-steering digital-to-analog converter DAC in 0.13 μm CMOS Technology. Master’s thesis, Fachhochslhule Technikum Karnten.
Gustavsson, M., Wikner, J., & Tan, N. (2000). CMOS data converter for communication. Boston: Kluwer Academic Publishers.
Hendriks, P. (1997). Specifying communication DACs. IEEE Spectrum, 34(7), 58–69.
Wang, H., Kao, H., & Lee, T. (2004). An 8-bit 2-V 2-mW 0.25-mm2 CMOS DAC. In IEEE Asia Conference on Advanced System Integrated Circuits (AP-ASIC2004), pp. 102–105.
Miquel Albiol, J. l. G., & Alarcón, E. (2004). Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters an extended design procedure. IEEE Transactions on Circuits and Systems, 51(1), 159–169.
Plas, A. V. D., & Vandenbussche, J. (1999). A 14-bit intrinsic accuyacy Q 2 random walk CMOS DAC. IEEE Journal of Solid-State Circuits, 34(12).
Wikner, J. (1999). Modeling of CMOS digital-to-analog converters for telecommunication. IEEE Transactions on Cicuits and Systems, 465, 1939–1944.
Zhou, Y., & Yuan, J. (2003). An 8-Bit 100-MHz CMOS Linear Interpolation DAC. IEEE J. Solid-State Circuits, 38(10), 1758–1761.