60th DRC. Conference Digest Device Research Conference

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From electron tubes to nanostructures: 60 years of electron device research
60th DRC. Conference Digest Device Research Conference - - Trang 3-8
H. Kroemer
This paper firstly gives a broad overview of electron device research from a perspective of technical conferences and their structure and organization. It then follows with a review of current and emerging technologies and their possible future developments. Subjects covered include: Moore's law; quantum devices; nanotechnology; nanoprinting; single electron devices; spintronics; low-temperature d...... hiện toàn bộ
#Electron tubes #Nanostructures #Electron devices #Corporate acquisitions #Microwave devices #Solid state circuits #Heterojunction bipolar transistors #Nanostructured materials #Radar #Microwave technology
Speed advantage of optimized metal S/D in 25 nm dual-gate fully-depleted CMOS
60th DRC. Conference Digest Device Research Conference - - Trang 77-78
D. Connelly, D. Grupp, D. Yergeau
With shrinking dimensions, control of extrinsic impedance is becoming increasingly performance limiting. Improvements to source/drain (S/D) technology thus become critical to technology scaling. Metal S/D is a promising approach. A doped S/D device was modeled with a two-component S/D profile: an ultra-steep extension profile offset from the gate edge, and a stronger primary S/D profile aligned to...... hiện toàn bộ
#Immune system #Delay #Degradation #Impedance #Contact resistance #MOS devices #CMOS technology #Virtual colonoscopy #Circuit simulation #Integrated circuit interconnections
RF noise in deep sub-/spl mu/m MOSFETs and proposed solution
60th DRC. Conference Digest Device Research Conference - - Trang 71-72
C.H. Huang, C.H. Lai, J.C. Hsieh, J. Liu, A. Chin
Anomalous dependence of finger number on noise figure (NF) is observed for 0.18 /spl mu/m and 0.13 /spl mu/m MOSFETs. A lowest NF of 0.93 dB is measured for 0.18 /spl mu/m MOSFET at 5.8 GHz using 50 fingers but increases with either increasing or decreasing finger number. The NF of 0.13 /spl mu/m devices have larger value and continuously decreases with increasing finger number. This is due to the...... hiện toàn bộ
#Radio frequency #MOSFETs #Noise measurement #Fingers #Frequency dependence #Circuit simulation #Electrical resistance measurement #Noise figure #Scattering parameters #Equivalent circuits
Graph-based quantum integrated circuits using III-V mulch-branch nanowire networks and their nano-Schottky gate control
60th DRC. Conference Digest Device Research Conference - - Trang 103-104
S. Kasai, M. Yumoto, T. Fukushi, T. Muranaka, H. Hasegawa
Beyond the scaling limit of Si CMOS LSls, one envisages nanoelectronics based on quantum devices. To realize quantum LSls (Q-LSIs), however, a novel architecture is required that is suitable to non-robust and charge-sensitive quantum devices which manipulate a single or a few electrons. The cascaded logic gate architecture in Si LSIs is utterly unsuitable. The purpose of this paper is to propose a...... hiện toàn bộ
#III-V semiconductor materials #Indium gallium arsenide #Nanoscale devices #Etching #Gallium arsenide #Electrons #Logic functions #Wire #Chemicals #Data structures
Device Research Conference (Cat. No.02TH8606)
60th DRC. Conference Digest Device Research Conference - - 2002
Presents the front cover and table of contents from the conference proceedings.
AlGaN/GaN current aperture vertical electron transistors
60th DRC. Conference Digest Device Research Conference - - Trang 31-32
I. Ben-Yaacov, Y.-K. Seck, S. Heikman, S.P. DenBaars, U.K. Mishra
Describes AlGaN/GaN current aperture vertical electron transistor (CAVET) structures. A CAVET consists of a source region separated from a drain region by an insulating layer containing a narrow aperture which is filled with conducting material. A device mesa is formed by reactive ion etching, and source contacts are deposited on either side of the aperture. The drain metal contacts the n-doped re...... hiện toàn bộ
#Aluminum gallium nitride #Gallium nitride #Apertures #Electrons #Insulation #Conducting materials #Etching #Breakdown voltage #MOCVD #Surface treatment
Electron inversion layer mobility in strained-Si n-MOSFETs with high channel doping concentration achieved by ion implantation
60th DRC. Conference Digest Device Research Conference - - Trang 43-44
H.M. Nayfeh, J.L. Hoyt, C.W. Leitz, A.J. Pitera, E.A. Fitzgerald, D.A. Antoniadis
Inversion layer mobility measurements in strained-Si n-MOSFETs fabricated using a typical MOSFET process including high temperature steps and with various channel doping concentrations, achieved by boron ion implantation, are compared with co-processed bulk-Si n-MOSFETs. It is found that a near-universal mobility relationship with vertical effective electric field, E/sub eff/, exists for strained-...... hiện toàn bộ
#Electron mobility #MOSFET circuits #Doping #Implants #Ion implantation #Materials science and technology #Temperature #Boron #Threshold voltage #Dielectric substrates
Structured cold point thermoelectric coolers
60th DRC. Conference Digest Device Research Conference - - Trang 125-128
U. Ghoshal
Solid-state thermoelectric coolers can revolutionize thermal management of electronics and optoelectronic systems, and small-scale refrigeration if the coolers could attain thermodynamic efficiency greater than 30% of the ideal Carnot cycle. The maximum temperature differential and the efficiency of thermoelectric coolers are known to depend on material properties through the thermoelectric figure...... hiện toàn bộ
#Thermoelectricity #Temperature dependence #Thermal conductivity #Thermal management of electronics #Transistors #Solid state circuits #Thermal management #Refrigeration #Thermodynamics #Material properties
Demonstration of FinFET CMOS circuits
60th DRC. Conference Digest Device Research Conference - - Trang 47-48
B.A. Rainey, D.M. Fried, M. Ieong, J. Kedzierski, E.J. Nowak
We present, to our knowledge, the first published experimental demonstration of a CMOS inverter chain built from FinFETs, completely integrated in 180nm CMOS technology, using one level of copper wiring and tungsten vias. A four-stage inverter chain with Lgate = 200nm, Tsi =, 60nm, and Tox = 2.2nm was run at 1.5V. We demonstrate successfully propagating CMOS levels through four inverter stages emp...... hiện toàn bộ
#FinFETs #Circuits #Inverters #CMOS technology #Etching #Electrodes #Implants #Silicides #Tungsten #Voltage
Thermal performance of metamorphic double heterojunction bipolar transistors with InP and InAlP buffer layers
60th DRC. Conference Digest Device Research Conference - - Trang 169-170
Y.M. Kim, M. Dahlstrom, M.J.W. Rodwell, A.C. Gossard
InP-based double heterojunction bipolar transistors (DHBT) are a key technology for high-speed optical fiber transmission. InP substrates are expensive and are not available in as large sizes as GaAs substrates. Moreover, InP substrates are fragile and are easily broken in fabrication. This motivates development of metamorphic InP DHBT (MDHBT) on GaAs. Thermal performance is of critical importance...... hiện toàn bộ
#Double heterojunction bipolar transistors #Indium phosphide #Buffer layers #Thermal resistance #Thermal conductivity #Gallium arsenide #Optical fibers #Optical device fabrication #Geometry #Temperature
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