Speed advantage of optimized metal S/D in 25 nm dual-gate fully-depleted CMOS

With shrinking dimensions, control of extrinsic impedance is becoming increasingly performance limiting. Improvements to source/drain (S/D) technology thus become critical to technology scaling. Metal S/D is a promising approach. A doped S/D device was modeled with a two-component S/D profile: an ultra-steep extension profile offset from the gate edge, and a stronger primary S/D profile aligned to the metal contact. The metal S/D was offset from the gate edge to improve the short channel margin. By reducing series resistance and allowing for lower fringe capacitance, a metal S/D device allows for substantial improvement in speed and/or power. An offset from the metal S/D to the gate should be used to reduce short channel effects. If doped S/D is used, then ultra-low resistance contacts are mandatory.