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60th DRC. Conference Digest Device Research Conference

 

 

 

 

Cơ quản chủ quản:  N/A

Các bài báo tiêu biểu

Structured cold point thermoelectric coolers
- Trang 125-128
U. Ghoshal
Solid-state thermoelectric coolers can revolutionize thermal management of electronics and optoelectronic systems, and small-scale refrigeration if the coolers could attain thermodynamic efficiency greater than 30% of the ideal Carnot cycle. The maximum temperature differential and the efficiency of thermoelectric coolers are known to depend on material properties through the thermoelectric figure... hiện toàn bộ
#Thermoelectricity #Temperature dependence #Thermal conductivity #Thermal management of electronics #Transistors #Solid state circuits #Thermal management #Refrigeration #Thermodynamics #Material properties
Tunneling through multi-layer gate dielectrics - an analytical model
- Trang 105-106
I. Polishchuk, Yee-Chia Yeo, Tsu-Jae King, Chenming Hu
We propose an analytical direct-tunneling model for multilayer gate dielectrics. This model predicts the amount of gate leakage current as a function of equivalent oxide thickness of the gate dielectric stack and the composition of the stack. This simple model is a useful tool in the development of future CMOS gate dielectric stacks.
#Tunneling #Dielectrics #Analytical models #Leakage current #Semiconductor device modeling #Electrons #Frequency #Voltage #Predictive models #CMOS integrated circuits
Room temperature grown zirconia/SiO/sub 2/ dielectric stacks with 1 nm EOT
- Trang 101-102
S. Ramanathan, P.C. McIntyre
Metal-oxide films such as zirconia and hafnia are currently being investigated to replace silicon dioxide as the gate dielectric material in future CMOS devices. It is important to develop processing science to grow these dielectric films of high electrical quality. Previously, we have grown zirconia films by ultraviolet ozone oxidation (UVO) on chemical oxide with electrical thickness ranging fro... hiện toàn bộ
#Temperature #Voltage #Stress #Semiconductor films #Dielectric thin films #Leakage current #Silicon #Dielectric films #Oxidation #Materials science and technology
Speed advantage of optimized metal S/D in 25 nm dual-gate fully-depleted CMOS
- Trang 77-78
D. Connelly, D. Grupp, D. Yergeau
With shrinking dimensions, control of extrinsic impedance is becoming increasingly performance limiting. Improvements to source/drain (S/D) technology thus become critical to technology scaling. Metal S/D is a promising approach. A doped S/D device was modeled with a two-component S/D profile: an ultra-steep extension profile offset from the gate edge, and a stronger primary S/D profile aligned to... hiện toàn bộ
#Immune system #Delay #Degradation #Impedance #Contact resistance #MOS devices #CMOS technology #Virtual colonoscopy #Circuit simulation #Integrated circuit interconnections
Reliability and ESD for high voltage LDMOS with SenseFET
- Trang 57-58
Y.S. Choi, J.J. Kim, C.K. Jeon, M.H. Kim, S.L. Kim, H.S. Kang, C.S. Song
This paper presents the structure and method of effective ESD protection and reliability in high voltage LDMOS with Sense Source (SenseFET) which is newly proposed 1-chip process for smart power ICs. This structure and method have been investigated experimentally and theoretically by employing two-dimensional process and device simulators. The cause of failure turned out to be Sense Source which i... hiện toàn bộ
#Electrostatic discharge #Protection #Semiconductor device reliability #MOSFETs #Resistors #Testing #Breakdown voltage #Contacts #Batteries #MOS devices
Contact printing with nanometer resolution
- Trang 149-150
Y.-L. Loo, R.L. Willett, K.W. Baldwin, J.A. Rogers
Developed a purely additive contact printing technique that can, in a single step, form complex patterns of functional materials with nanometer resolution. This method can print directly nanostructures without the use of sacrificial resists, etching procedures or post-patterning deposition steps that are often required with other nanolithographic techniques. It is operationally simple, compatible ... hiện toàn bộ
#Printing #Dielectric materials #Nanostructured materials #Dielectric substrates #Metal-insulator structures #Organic thin film transistors #Additives #Nanostructures #Resists #Etching
RF noise in deep sub-/spl mu/m MOSFETs and proposed solution
- Trang 71-72
C.H. Huang, C.H. Lai, J.C. Hsieh, J. Liu, A. Chin
Anomalous dependence of finger number on noise figure (NF) is observed for 0.18 /spl mu/m and 0.13 /spl mu/m MOSFETs. A lowest NF of 0.93 dB is measured for 0.18 /spl mu/m MOSFET at 5.8 GHz using 50 fingers but increases with either increasing or decreasing finger number. The NF of 0.13 /spl mu/m devices have larger value and continuously decreases with increasing finger number. This is due to the... hiện toàn bộ
#Radio frequency #MOSFETs #Noise measurement #Fingers #Frequency dependence #Circuit simulation #Electrical resistance measurement #Noise figure #Scattering parameters #Equivalent circuits
An enhanced compact waffle MOSFET for RF integrated circuits
- Trang 73-74 - 2002
Sang Lam, Wing Hung Ki, P.K. Ko, Mansun Chan
Several layout methods have been proposed to increase the compactness of a MOSFET. Among the methods, the waffle layout has been mentioned most in the literature. Nevertheless, it has not been commonly used since its inception. This is simply due to the deficiencies associated with the traditional waffle layout in submicron CMOS technology. In this paper, an enhanced compact and expandable waffle ... hiện toàn bộ
#MOSFET circuits #Radio frequency #Radiofrequency integrated circuits #Fingers #Performance gain #Transconductance #Parasitic capacitance #CMOS technology #Circuit testing #CMOS process
Nano-scale implantless Schottky-barrier SOI FinFETs with excellent ambipolar performance
- Trang 45-46
Horng-Chih Lin, Meng-Fan Wang, Fu-Ju Hou, Jan-Tsai Liu, Fu-Hsiang Ko, Hsuen-Li Chen, Guo-Wei Huang, Tiao-Yuan Huang, S.M. Sze
A novel nano-scale SOI device featuring silicide Schottky source/drain and field-induced S/D extensions is proposed and demonstrated. Excellent p- and n-channel performance with nearly ideal subthreshold swing (/spl sim/ 60 mV/dec.) and high on-/off-state current ratio (>10/sup 9/ and >10/sup 8/ for n- and p-channel modes, respectively) is realized, for the first time, on a single device. These en... hiện toàn bộ
#FinFETs #Silicides #Etching #Fabrication #Voltage #Nanoscale devices #Fluctuations #Lithography #Doping #Oxidation
Polymer LEDs and lasers for integrated optics
- Trang 145
M.D. McGehee
Summary form only given. Polymer LEDs and lasers are attractive for integrated optics because they can be easily deposited from solution by spin coating, inkjet printing or screen printing techniques onto just about any substrate. The best polymer LEDs now have high efficiencies (> 4 %), brightnesses of 100 Cd/m/sup 2/ at 3-4 V and lifetimes longer than 10,000 hours. Several companies are beginnin... hiện toàn bộ
#Organic light emitting diodes #Integrated optics #Polymers #Coatings #Brightness #Manufacturing #Distributed feedback devices #Diode lasers