Improved MOSFET electron mobility model for advanced gate dielectric stacks

The scaling of CMOS technology requires continued reduction in the capacitance equivalent thickness (CET) of the gate dielectric. Since scaling of pure Si02 to thicknesses less than 12 .& becomes problematic due to the increased tunneling current, it is necessary to incorporate a material with a higher dielectric constant into the gate stack. Integration of `true high-K´ dielectrics, such as ZrO] or HQ, into a CMOS process flow still remains a major challenge. In contrast, an oxynitride/Si3N4 gate dielectric stack has been demonstrated in high-performance MOSFETs with the thinnest CET (7A) reported to date [I]. Therefore, Si3N4 and oxynitrides will likely be the most important gate dielectric aterials during this decade. Although alternative gate dielectrics suppress gate leakage current, they can degrade carrier channel mobility. In this work, we propose a quantitative model for electron mobility in MOSFETs with oxynitride/Si,N, gate dielectric. We also show that electron mobility is directly related to the nitrogen content in the dielectric film and to the fabrication conditions.