Proceedings. IEEE Asia-Pacific Conference on ASIC,

In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2 K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The (255,239) RS decoder is implemented by 0.25 /spl mu/m CMOS 1P5M standard cells with gate counts of 32.9 K and area of 2.03 mm/sup 2/. Simulation results show our approach can work successfully at the data rate of 2.5-Gbps and achieve 80% reduction of power dissipation on the average.

We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 /spl mu/m CMOS technology, a 200 MHz clock is easily achieved, and the throughput rate is 2.381 Gbps for 128-bit keys, 2.008 Gbps for 192-bit keys, and 1.736 Gbps for 256-bit keys. Testability of the design also is considered. The hardware cost of the AES design is about 58.5 K gates.

In this paper, a novel block channel equalization design for wireless communication over mobile radio channels with both inter-symbol interference (ISI) and Rayleigh fading is presented. The proposed design consists of a matched filter, a channel estimator and a block decision feedback equalizer (BDFE). The channel estimator, which is based on a revised RLS algorithm, adopts a semi-blind approach. The estimated channel impulse response h(n) is used later in both matched filtering and the BDFE update. The BDFE actually consists of a noise whitener and a maximum-likelihood block detector followed by a symbol detector. The filter coefficients of the BDFE are calculated subject to the Cholesky factorization and are updated once for each data block. Various wireless channel models, covering ISI and Rayleigh fading, have been simulated to demonstrate the effectiveness of the proposed equalization scheme. Based on this scheme, a novel systolic array design is next developed. The derived equalizer design features a highly parallel, hardware efficient and scalable design. Implementation results on a Xilinx XCV600 FPGA indicate an up-to-3-million symbols per second processing rate at 35 MHz working frequency.

An automatic hardware generator is developed for computing multiplier-based arithmetic functions. The generator can produce Verilog codes of parallel multipliers/multiplier-accumulator/inner product calculator and their corresponding test fixture files for pre-layout simulation. The irregular connection of the Wallace tree in the parallel multiplier is optimized in order to reduce the critical path delay. In addition to the conventional 3:2 counter that is usually included in standard cell library, our generator can select other different compression elements that are designed using the full-custom approach based on pass-transistor logic. Thus, our multiplier generator combines the advantages of three basic design methodologies: high-level synthesis, cell-based design, full-custom design along with area/time optimization.

Bài báo này trình bày một bộ phát DS-CDMA hoàn toàn kỹ thuật số cho đường lên và một bộ thu cơ sở đầu cuối cho các mạng cáp/HFC. Bộ phát đường lên hỗ trợ tính linh hoạt tần số của sóng mang, các chòm sao QPSK và QAM lên đến 64QAM, tốc độ ký hiệu biến đổi từ 160kchip/s đến 5.12Mchip/s, tăng gấp đôi theo lũy thừa, và chuyển đổi lên số trực tiếp để đạt được độ chính xác trong biên độ và pha điều chế. Bộ phát bao gồm bộ lọc định hình xung, bộ lọc bán băng, bộ lọc tích hợp-cắt (CIC) chuỗi, và bộ lọc SINC ngược. Bộ thu cơ sở đầu cuối hoàn toàn kỹ thuật số hỗ trợ điều chế biên độ vuông có thể lập trình lên đến 64QAM. Các thuật toán phục hồi thời gian và sóng mang nhanh được áp dụng cho truyền tải chế độ burst. Việc định vị mã có thể đạt được trong vòng 2 ký hiệu, và việc định vị sóng mang có thể đạt được trong vòng 31 ký hiệu. Phục hồi thời gian hoàn toàn kỹ thuật số được thiết kế với khả năng dung sai sai lệch thời gian ký hiệu /spl plusmn/200ppm và phục hồi sóng mang có thể bù trừ /spl plusmn/100ppm của sai lệch tần số sóng mang.

A fast 64 bit parallel binary adder for high performance microprocessors and DSP processors is described. It is implemented in UMC 2.5 V 0.25 /spl mu/m 1-poly 5-metal CMOS technology. A new adder architecture with four stages of dynamic logic is proposed, based on the modification of Kogge and Stone algorithm. Efficiently using dynamic compound gates, clock-delayed dynamic logic and FET scaling technique, the new adder architecture achieved good performance. The addition latency is 700 ps, 20% faster than that of the conventional architecture adder. The area of the adder is 0.16 mm/sup 2/, similar to that of the conventional one.

In this paper, an efficient VLSI architecture to compute the n-bit Montgomery modular multiplication is proposed. By using the staged carry save adder (CSA) array, the computation cycles of addition reduced by about 3n/8. In addition, we apply the switch unit to save 2Q-2 registers from the traditional Q-bit CSA. Compare with the original method, the total clock cycles can be reduced by 68% in the case of n=1024 and Q=512 bits.

In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large area on an IC chip, being different from the conventional one. The proposed filter needs smaller area than the conventional one under the condition of Q > 2. The proposed circuit is simulated by SPICE to confirm its characteristics.

Two new high-speed class AB buffer amplifiers with accurate quiescent current control, which are suitable for output driver applications, are proposed. The buffer amplifiers draw little current during static but have large driving capability during transients. They have been demonstrated with the TSMC 0.35 /spl mu/m CMOS technology.

This paper presents a programmable gain amplifier (PGA) for a dual band (GSM900/DCS1800) low-IF receiver. It uses a negative feedback approach to achieve the high linearity requirement. In addition to the amplifier, anti-alias filtering and DC offset removal are included for the subsequent IF signal processing. A dual-bandwidth algorithm is developed to speed up the settling time on DC removal. A modified Sallen-Key filter helps to provide better than 40 dB anti-aliasing and blocker attenuation near the sampling frequency of 13 MHz. The overall PGA gain varies from 0 dB to 46 dB with 2 dB per step. With a 0.25 /spl mu/m CMOS process, this device dissipates 10.3 mW from a 2.7 V supply voltage.