Proceedings. IEEE Asia-Pacific Conference on ASIC,

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A low-power Reed-Solomon decoder for STM-16 optical communications
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 351-354
Hsie-Chia Chang, Chien-Ching Lin, Chen-Yi Lee
In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2 K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a termina...... hiện toàn bộ
#Reed-Solomon codes #Decoding #Polynomials #Optical fiber communication #Equations #Energy consumption #Proposals #Computational modeling #Circuit simulation #Power dissipation
A high-throughput low-cost AES cipher chip
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 85-88
Tsung-Fu Lin, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu
We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 /spl mu/m CMOS technology, a 200 MHz clock i...... hiện toàn bộ
#Elliptic curve cryptography #Hardware #CMOS technology #Clocks #Application specific integrated circuits #Table lookup #Laboratories #Costs #Internet #Communication system security
A novel block equalization design for wireless communication with ISI and Rayleigh fading channels
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 291-294
Yin-Tsung Hwang, Jing-Yi Liu, Chi-Cheng Han, Chien-Hsing Wu
In this paper, a novel block channel equalization design for wireless communication over mobile radio channels with both inter-symbol interference (ISI) and Rayleigh fading is presented. The proposed design consists of a matched filter, a channel estimator and a block decision feedback equalizer (BDFE). The channel estimator, which is based on a revised RLS algorithm, adopts a semi-blind approach....... hiện toàn bộ
#Wireless communication #Intersymbol interference #Fading #Rayleigh channels #Matched filters #Detectors #Land mobile radio #Decision feedback equalizers #Resonance light scattering #Filtering
A high performance function generator for multiplier-based arithmetic operations
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 331-334
Tso-Bing Juang, Jeng-Hsin Jan, Ming-Yu Tsai, Shen-Fu Hsiao
An automatic hardware generator is developed for computing multiplier-based arithmetic functions. The generator can produce Verilog codes of parallel multipliers/multiplier-accumulator/inner product calculator and their corresponding test fixture files for pre-layout simulation. The irregular connection of the Wallace tree in the parallel multiplier is optimized in order to reduce the critical pat...... hiện toàn bộ
#Signal generators #Arithmetic #Hardware design languages #Testing #Fixtures #Computational modeling #Delay #Counting circuits #Libraries #Logic design
Bộ phát DS-CDMA kỹ thuật số hoàn toàn và thiết kế VLSI cơ sở của bộ thu đầu cuối cho mạng cáp đầu lên Dịch bởi AI
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 371-374
Keng-Yi Su, Muh-Tain Shieu, Chorng-Kuang Wang
Bài báo này trình bày một bộ phát DS-CDMA hoàn toàn kỹ thuật số cho đường lên và một bộ thu cơ sở đầu cuối cho các mạng cáp/HFC. Bộ phát đường lên hỗ trợ tính linh hoạt tần số của sóng mang, các chòm sao QPSK và QAM lên đến 64QAM, tốc độ ký hiệu biến đổi từ 160kchip/s đến 5.12Mchip/s, tăng gấp đôi theo lũy thừa, và chuyển đổi lên số trực tiếp để đạt được độ chính xác trong biên độ và pha điều chế....... hiện toàn bộ
#Giao tiếp đa truy cập #Bộ phát #Cơ sở #Tích hợp quy mô rất lớn #Bộ lọc #Thời gian #Tần số #Điều chế biên độ vuông #Cáp quang lai đồng trục #Khóa pha điều chế điều chế biên độ vuông
A 64 bit parallel CMOS adder for high performance processors
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 205-208
Sun Xu-guang, Mao Zhi-gang, Lai Feng-chang
A fast 64 bit parallel binary adder for high performance microprocessors and DSP processors is described. It is implemented in UMC 2.5 V 0.25 /spl mu/m 1-poly 5-metal CMOS technology. A new adder architecture with four stages of dynamic logic is proposed, based on the modification of Kogge and Stone algorithm. Efficiently using dynamic compound gates, clock-delayed dynamic logic and FET scaling te...... hiện toàn bộ
#CMOS process #Adders #CMOS technology #Computer architecture #Microelectronics #Digital signal processing #CMOS logic circuits #Clocks #Delay #FETs
A staged carry-save-adder array for Montgomery modular multiplication
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 97-100
Jhing-Fa Wang, Po-Chuan Lin, Ping-Kun Chiu
In this paper, an efficient VLSI architecture to compute the n-bit Montgomery modular multiplication is proposed. By using the staged carry save adder (CSA) array, the computation cycles of addition reduced by about 3n/8. In addition, we apply the switch unit to save 2Q-2 registers from the traditional Q-bit CSA. Compare with the original method, the total clock cycles can be reduced by 68% in the...... hiện toàn bộ
#Hardware #Clocks #Costs #Switches #Public key cryptography #Cities and towns #Computer architecture #Data security #Modems #Digital signatures
A CMOS current-mode band-pass filter with small chip area
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 13-16
Y. Maruyama, A. Hyogo, K. Sekine
In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large are...... hiện toàn bộ
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
High-speed class AB buffer amplifiers with accurate quiescent current control
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 157-160
Chih-Wen Lu, Meng-Lieh Sheu
Two new high-speed class AB buffer amplifiers with accurate quiescent current control, which are suitable for output driver applications, are proposed. The buffer amplifiers draw little current during static but have large driving capability during transients. They have been demonstrated with the TSMC 0.35 /spl mu/m CMOS technology.
#Current control #Mirrors #Voltage #Electric current control #Driver circuits #CMOS technology #Displays #Operational amplifiers #Transconductance #Power supplies
A CMOS low-IF programmable gain amplifier with speed-enhanced DC offset cancellation
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 133-136
Chao-Shiun Wang, Po-Chiun Huang
This paper presents a programmable gain amplifier (PGA) for a dual band (GSM900/DCS1800) low-IF receiver. It uses a negative feedback approach to achieve the high linearity requirement. In addition to the amplifier, anti-alias filtering and DC offset removal are included for the subsequent IF signal processing. A dual-bandwidth algorithm is developed to speed up the settling time on DC removal. A ...... hiện toàn bộ
#Electronics packaging #Signal processing algorithms #Dual band #Negative feedback #Linearity #Filtering #Filters #Attenuation #Signal sampling #Frequency
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