Proceedings. IEEE Asia-Pacific Conference on ASIC,

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An all-digital PLL clock multiplier
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 275-278
T. Olsson, P. Nilsson
A fully integrated digital PLL used as a clock multiplying circuit is designed and manufactured. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 /spl mu/m standard CMOS process and a 3.0 V supply voltage, the PLL has a frequency range of 152 MHz to 366 MHz an...... hiện toàn bộ
#Phase locked loops #Clocks #Ring oscillators #Frequency #Filters #Detectors #Software libraries #Counting circuits #Digital control #Delay
The CMOS on-chip oscillator based on level tracking technique
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 197-200
Chia-Yang Chang, Po-Chang Chen, Ching-Yang Yang, Yang-Han Lee
In this paper, we propose the architecture of a CMOS fully integrated level-locked loop (LLL). A 455 kHz LLL without external reference signal achieves the target of 1 percent variation, and consumes 9 mW with 3.6 V power supply in a standard 0.5 /spl mu/m CMOS process. The frequency-to-voltage converter (FVC) in the LLL, built upon the charge redistribution principle, can decrease the process var...... hiện toàn bộ
#Power supplies #Voltage-controlled oscillators #Target tracking #Signal processing #CMOS process #Frequency conversion #Programmable control #Delay effects #Circuit noise #Regulators
Spread-spectrum clocking in switching regulators to reduce EMI
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 141-144
H. Sadamura, T. Daimon, T. Shindo, H. Kobayashi, T. Myono, T. Suzuki, S. Kawai, T. Iijima
This paper describes a simple, inexpensive technique for intentionally broadening and flattening the spectrum of a DC-DC converter (switching regulator) to reduce electromagnetic interference (EMI). This noise spectrum broadening technique involves intentionally introducing pseudorandom dithering of control clock timing, which can be achieved by adding simple digital circuitry. This technique can ...... hiện toàn bộ
#Spread spectrum communication #Clocks #Regulators #Electromagnetic interference #Circuit noise #DC-DC power converters #Noise reduction #Circuit testing #Switching converters #Timing
Automatic Verilog code generation of an 8-bit RISC micro-controller
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 327-330
Yun-Tai Husueh, Wen-Chung Chang, Jui-Min Lai
In this paper, we describe a design method, which can automatically generate Verilog code for an 8-bit RISC microcontroller with a user-defined instruction set. With this method, one can shorten the development time, increase the efficiency of Verilog coding, and decrease the man-hour requirement. Most of all, even those who do not have the knowledge and techniques of a Verilog coding for a RISC m...... hiện toàn bộ
#Hardware design languages #Reduced instruction set computing #Design methodology #Databases #Automatic control #Pipelines #Decoding #Algorithms #Automatic generation control #Debugging
A high performance class AB CMOS rail to rail voltage follower
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 161-163
P. Boonyaporn, V. Kasemsuwan
A high performance class AB CMOS rail to rail voltage follower is presented. The circuit is based on the symmetrical class AB voltage follower and can operate under supply voltages of /spl plusmn/1.5 V. The proposed circuit has power dissipation of 2.5 mW under quiescent condition and can drive /spl plusmn/1.2 V to 250 /spl Omega/ load with a total harmonic distortion of less than 0.6 percent and ...... hiện toàn bộ
#Voltage #Power dissipation #MOSFETs #CMOS technology #Impedance #Drives #Harmonic distortion #Circuit stability #Joining processes #MOS devices
A VLSI architecture of DMT based transceiver for VDSL system
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 363-366
Ching-Chi Chang, Muh-Tian Shieu, Chorng-Kuang Wang
This paper presents a VLSI architecture of the transceiver for DMT-VDSL system with data rate as high as 52 Mbps. Consisting of four radix-2 stages and three radix2/4/8 stages, a variable length pipelined architecture of FFT/IFFT compatible with 5 modes is proposed to perform the DMT modulation/demodulation. Based on LMS adaptation algorithm, time domain equalizer (TEQ) and frequency domain equali...... hiện toàn bộ
#Very large scale integration #OFDM modulation #Transceivers #Crosstalk #DSL #Radiofrequency interference #Radio broadcasting #Transmitters #Data engineering #Least squares approximation
A sub-word parallel digital signal processor for wireless communication systems
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 287-290
Yuan-Hao Huang, Tzi-Dar Chiueh
In this paper, we propose a programmable fixed-point digital signal processor for wireless communications. The architecture of the processor is designed according to the computation requirements of modern communication systems. A decimation-in-frequency (DIF) butterfly unit is built in the processor to enhance the processing capability of FFT operations needed in orthogonal-frequency-division-mult...... hiện toàn bộ
#Digital signal processors #Wireless communication #Computer architecture #Process design #OFDM #Acceleration #Viterbi algorithm #Signal processing #Signal processing algorithms #Transceivers
High performance 1 V 2.4 GHz CMOS VCO
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 185-188
N. Troedsson, H. Sjoland
A low phase noise 2.4 GHz voltage controlled oscillator (VCO) with 1 V supply is presented. The VCO is based on the differential negative resistance oscillator with the tail current source replaced by an inductor. The inductor both improves the noise factor of the oscillator and enables maximum voltage swing over the tank. The amplitude limitation which is usually set by the tail current source is...... hiện toàn bộ
#Voltage-controlled oscillators #Phase noise #Tail #Inductors #Voltage control #Power measurement #Voltage measurement #Frequency measurement #Noise measurement #Phase measurement
A 2.5 Gbps CMOS laser diode driver with preemphasis technique
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 65-68
Guo-Cheng Chen, Wei-Zen Chen, Ren-Hong Luo
This paper describes the design of a 2.5 Gbps laser diode (LD) driver circuit in a 0.35/spl mu/m digital CMOS process. The LD driver delivers a biased current range from 5 to 10 mA and a modulation current of 20 mA. The biased current is programmable by a 3-bit D/A. High current driving capability as well as agile switching speed are achieved by inductive peaking and preemphasis techniques. Operat...... hiện toàn bộ
#Diode lasers #Driver circuits #High speed optical techniques #Optical modulation #Power control #Optical design #Stimulated emission #Threshold current #Preamplifiers #CMOS process
A low power CMOS adaptive line equalizer for fast Ethernet
Proceedings. IEEE Asia-Pacific Conference on ASIC, - - Trang 129-132
Kwisung Yoo, Hoon Lee, Gunhee Han
An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed adaptive equalizer is designed for the 0.35 /spl mu/m CMOS process. The designed equalizer has low power consumption (19 mW) and small silicon area (0.07 mm/sup 2/).
#Ethernet networks #Communication cables #Bandwidth #Filters #Transfer functions #Frequency #Adaptive equalizers #Poles and zeros #Circuits #Data communication
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