An all-digital PLL clock multiplier

A fully integrated digital PLL used as a clock multiplying circuit is designed and manufactured. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 /spl mu/m standard CMOS process and a 3.0 V supply voltage, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm/sup 2/. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system process change simulation.