Proceedings. IEEE Asia-Pacific Conference on ASIC,
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A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large are......
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
Voltage controlled ring oscillator with wide tuning range and fast voltage swing
- Trang 201-204
A new design of a voltage controlled ring oscillator is proposed. The proposed design allows an implementation of a low frequency ring oscillator using relatively small devices and less stages. A voltage controlled ring oscillator with tuning range from 40 Hz to 380 MHz is achieved using the proposed method. In addition, the proposed circuit enables the output voltage to swing faster than the conv......
#Voltage-controlled oscillators #Voltage control #Ring oscillators #Tuning #Frequency #Circuits #Inverters #Delay #Equations #Variable structure systems
A 33 mW 12-bit 100 MHz sample-and-hold amplifier
- Trang 169-172
A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 /spl mu/m CMOS technology, the SHA achieves 73 dB SFDR for 2 Vpp input at 100 MHz samp......
#Sampling methods #Clocks #Capacitors #Switches #Analog-digital conversion #CMOS technology #Frequency #Signal resolution #Bandwidth #Voltage
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
- Trang 359-362
This paper presents the VLSI design of a reconfigurable multimode Reed Solomon (RS) codec for various high-speed communication systems. Our decoder design is based on the Euclidean algorithm such that the datapath units are regular and simple. With its ability to support a variety of (n, k, t) RS specifications (0/spl les/t/spl les/8) and (0/spl les/n/spl les/255), this RS codec design is suitable......
#Very large scale integration #Reed-Solomon codes #Codecs #CMOS technology #Decoding #Algorithm design and analysis #Modems #Clocks #Frequency #Data processing
Self-isolated gain-enhanced sense amplifier
- Trang 57-60
The work describes a self-isolated gain-enhanced sense amplifier (SGSA) for high-speed memory. A pair of incoming signals with large capacitive load can be self-isolated to the input nodes of the SGSA during the transient operation. The input nodes of the SGSA are then regenerated through the self-feedback control of the sense amplifier. Thus the gain is enhanced and the speed and driving capabili......
#Random access memory #Logic circuits #Feedback #Differential amplifiers #Very large scale integration #High speed integrated circuits #Laboratories #Operational amplifiers #Signal design #Integrated circuit interconnections
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
- Trang 1-4
In this paper, a very low-voltage fourth-order bandpass delta-sigma modulator with a two-path architecture is presented. Using the modified switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without any voltage multiplier or bootstrapping switch. Realized in a 0.25 /spl mu/m 1P5M standard CMOS process, the prototype modulator exhibits a signal-to-noise-plus-dist......
#Delta modulation #Low voltage #Clocks #Transfer functions #Switching circuits #Voltage control #Band pass filters #Signal processing #Feedback circuits #Sampling methods
A 64 bit parallel CMOS adder for high performance processors
- Trang 205-208
A fast 64 bit parallel binary adder for high performance microprocessors and DSP processors is described. It is implemented in UMC 2.5 V 0.25 /spl mu/m 1-poly 5-metal CMOS technology. A new adder architecture with four stages of dynamic logic is proposed, based on the modification of Kogge and Stone algorithm. Efficiently using dynamic compound gates, clock-delayed dynamic logic and FET scaling te......
#CMOS process #Adders #CMOS technology #Computer architecture #Microelectronics #Digital signal processing #CMOS logic circuits #Clocks #Delay #FETs
A dual-loop automatic gain control for infrared communication system
- Trang 125-128
This paper presents a dual-loop automatic gain control (AGC) employed in a 10 Mbps infrared communication system. The AGC is composed of an exponential-type variable-gain amplifier, a shaping filter, a gain/buffer stage, a noncoherent envelope detector, and a pair of integrators that provide dual loop bandwidths. The switch and two integrators are realized by a proposed switched integrator techniq......
#Gain control #Optical fiber communication #Circuits #Bandwidth #Optical receivers #Optical filters #Signal processing #Detectors #High speed optical techniques #Switches
A novel systolic VLSI architecture for fast RSA modular multiplication
- Trang 81-84
In this paper, we present a novel systolic VLSI architecture for performing fast modular multiplication in RSA cryptosystem. First, we propose a modified version of Montgomery's modular multiplication algorithm using a precomputed addition result, and then the proposed algorithm is mapped onto linear systolic arrays of processing elements for modular multiplication. Our implementation results have......
#Very large scale integration #Public key cryptography #Computer architecture #Hardware #Systolic arrays #Computer science #Data communication #Business #Digital signatures #Arithmetic
A real-time lipreading LSI for word recognition
- Trang 303-306
In the paper, we present a real-time lip-reading LSI for recognizing spoken words from lip movement. The LSI recognizes up to 8 words based on the hidden Markov model (HMM). The LSI accepts the 256/spl times/256 8-bit gray-scale images from a camera, and outputs the 3-bit symbol code of words for 43 images (corresponding to 1.53 s). We present a lip-reading algorithm optimized for hardware impleme......
#Large scale integration #Hidden Markov models #Image edge detection #Gray-scale #Cameras #Speech recognition #Humans #Vector quantization #Hardware design languages #Image recognition