Proceedings. IEEE Asia-Pacific Conference on ASIC,
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Các bài báo tiêu biểu
A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip
area. Q (quality factor) of the proposed filter can be mostly determined by the
ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of
the values of two capacitance similar to the conventional band-pass filter.
Therefore, the proposed filter does not need large capacitance that occupies
large are...
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
Transfer function design of stable high-order sigma-delta modulators with root locus inside unit circle
- Trang 5-8
In this paper, a systematic method to design stable high-order sigma-delta
modulator (SDM) transfer functions, with no need of stability mechanisms, is
proposed. It is shown that a high-order SDM can be absolutely stable if the
departure angles of the root locus of its noise-shaping function are properly
designed. Tradeoffs between stability and performance of the SDMs are presented.
#Transfer functions #Delta-sigma modulation #H infinity control #Gain #Noise shaping #Cities and towns #Stability analysis #Ear #Linear systems #Signal to noise ratio
Design of a DMT-based baseband transceiver for very-high-speed digital subscriber lines
- Trang 367-370
In this paper, we propose a transceiver design for the ETSI VDSL standard that
uses the discrete multi-tone (DMT) modulation. Algorithms for channel
estimation/equalization, symbol synchronization, sampling clock tracking are
designed and integrated into the receiver architecture. Fixed-point simulation
of the whole system shows that the proposed receiver architecture is capable of
very high-rate ...
#Baseband #Transceivers #DSL #Telecommunication standards #OFDM modulation #Channel estimation #Synchronization #Sampling methods #Clocks #Algorithm design and analysis
A low-distortion and swing-suppression sigma-delta modulator with extended dynamic range
- Trang 9-12
This work presents a novel low-distortion and swing-suppression second-order
sigma-delta modulator with extended dynamic range. The proposed modulator is
based on the dual-quantizer architecture and can effectively extend dynamic
range by only adding two simple digital filters in the digital circuit. The
technique for low-distortion and swing-suppression of the modulator are also
proposed. Accordi...
#Delta-sigma modulation #Dynamic range #Circuit topology #Wideband #Transfer functions #Bandwidth #Analog circuits #Quantization #Very large scale integration #Frequency
0.9-V sense-amplifier-based reduced-clock-swing MTCMOS flip-flops
- Trang 271-274
Scaling-down V/sub DD/ as well as adopting a reduced-swing clock simultaneously
is the key technique proposed in this work which results in remarkable power
reduction for VLSI chips. Several configurations of 0.9-V MTCMOS
(multi-threshold CMOS) flip-flops with reduced clock-swing (RCSFFs) are
investigated in this work. By using the MVT technique, and the pulsed-low
reduced-swing clock, the perform...
#Flip-flops #Clocks #Energy consumption #Threshold voltage #MOS devices #CMOS technology #Wires #Pulse circuits #Master-slave #Latches
A novel block equalization design for wireless communication with ISI and Rayleigh fading channels
- Trang 291-294
In this paper, a novel block channel equalization design for wireless
communication over mobile radio channels with both inter-symbol interference
(ISI) and Rayleigh fading is presented. The proposed design consists of a
matched filter, a channel estimator and a block decision feedback equalizer
(BDFE). The channel estimator, which is based on a revised RLS algorithm, adopts
a semi-blind approach....
#Wireless communication #Intersymbol interference #Fading #Rayleigh channels #Matched filters #Detectors #Land mobile radio #Decision feedback equalizers #Resonance light scattering #Filtering
A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique
- Trang 181-184
A CMOS comparator operating over a 1 V to 5 V supply range is presented. No
special low-voltage technology is used for fabrication. An experimental chip was
fabricated using a 0.5 /spl mu/m 5 V CMOS double-poly double-metal technology.
The chip area of the comparator was 230/spl times/160 /spl mu/m/sup 2/. Measured
results at 1 V supply voltage show a comparator response time of less than 4
/spl m...
#Preamplifiers #Sampling methods #Parasitic capacitance #Switches #CMOS technology #Low voltage #Energy consumption #Capacitors #Semiconductor device measurement #Time measurement
The noise and linearity optimization for a 1.9-GHz CMOS low noise amplifier
- Trang 253-257
For radio frequency integrated circuits (RFICs), and especially for low noise
amplifiers (LNAs), noise and linearity performances are critical
characteristics. A detailed analysis of noise and linearity for the cascode
architecture, a widely used circuit structure in LNA designs, is presented in
this paper. The noise and the linearity improvement techniques for cascode
structures are also develope...
#Linearity #Low-noise amplifiers #Integrated circuit noise #MOSFET circuits #Radiofrequency amplifiers #Radiofrequency integrated circuits #Computer architecture #Computer simulation #Performance analysis #Computational modeling
An 8-way VLIW embedded multimedia processor with advanced cache mechanism
- Trang 213-216
An 8-way VLIW embedded multimedia processor is developed in 0.11 /spl mu/m
7-layer Cu/Al metal CMOS process technology. The processor achieved the peak
performance of 2132 MIPS/2.1 GFLOPS/4.26 GOPS at 533 MHz. This processor equips
4-way integer and 4-way floating/media pipelines. Each media pipeline can
execute a 4-parallel SIMD instruction, so 16-operations can be executed at a
cycle. It also eq...
#VLIW #Pipelines #Laboratories #Energy consumption #CMOS process #Decoding #Microprocessors #Circuits #CMOS technology #Process design
A sub-word parallel digital signal processor for wireless communication systems
- Trang 287-290
In this paper, we propose a programmable fixed-point digital signal processor
for wireless communications. The architecture of the processor is designed
according to the computation requirements of modern communication systems. A
decimation-in-frequency (DIF) butterfly unit is built in the processor to
enhance the processing capability of FFT operations needed in
orthogonal-frequency-division-mult...
#Digital signal processors #Wireless communication #Computer architecture #Process design #OFDM #Acceleration #Viterbi algorithm #Signal processing #Signal processing algorithms #Transceivers