Proceedings. IEEE Asia-Pacific Conference on ASIC,

In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large area on an IC chip, being different from the conventional one. The proposed filter needs smaller area than the conventional one under the condition of Q > 2. The proposed circuit is simulated by SPICE to confirm its characteristics.

In this paper the AEC (acoustic echo canceller) is designed and implemented using VHDL. The designed echo canceller employs a pipeline and master-slave structure, and is realized with FPGA. As an adaptive algorithm, the normalized LMS algorithm is used. For coefficient adjustment, the stochastic iteration algorithm (SIA) which uses only current residual values is used and the number of registers are evidently reduced and convergence speed is also much improved compared to existing methods by using an embedded array block of FPGA for the FIR filter structure of the transceiver. The designed echo canceller is verified with the test board implemented for this paper. With the top-down design and synthesis using VHDL, the design time is reduced and modular design is achieved.

In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2 K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The (255,239) RS decoder is implemented by 0.25 /spl mu/m CMOS 1P5M standard cells with gate counts of 32.9 K and area of 2.03 mm/sup 2/. Simulation results show our approach can work successfully at the data rate of 2.5-Gbps and achieve 80% reduction of power dissipation on the average.

An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed adaptive equalizer is designed for the 0.35 /spl mu/m CMOS process. The designed equalizer has low power consumption (19 mW) and small silicon area (0.07 mm/sup 2/).

In this paper, a high-speed, low-complexity implementation of a data weighted averaging (DWA) algorithm is presented. Different from other published implementations, the maximum speed-limited function of the DWA algorithm, decoding for control signal generation and adding for register value updating, are replaced by carry look-ahead and rotating. Additionally, register simplification is adopted to reduce area costs. This design, in 0.25 /spl mu/m CMOS, for a 3-bit 8-element example can operate at a 800 MHz clock rates for post-layout simulations, and costs only 254 transistors.

A novel logarithmic response 0.25 /spl mu/m CMOS image sensor technology for high output swing and low noise error is proposed. The experimental results show that the new cell has 4 times higher output voltage swing. Optimized simulation results show 6.5 times larger output voltage swing, which is achievable for an input signal range of 0.01 lux to 100,000 lux. With this wider swing, the effect of fixed pattern noise (FPN) reflecting on the digital output can be reduced significantly. In addition, after adding a correlated double sampling (CDS) control transistor, the output voltage difference variation due to FPN is greatly reduced from 73 mV to 15 mV.

A new four-phase charge pumping circuit for low supply voltages using 0.6 /spl mu/m triple-well CMOS technology to generate high negative boosted voltages is presented. With the new substrate connected technique, the influence of threshold voltage (-0.94 V) is minimized and the body effect is almost eliminated. A five-stage charge pump can efficiently pump lower than -7 V at supply voltage of 1.8 V with 100 /spl mu/A loading current.

The characteristics of on-chip inductors such as the S parameter, the quality factor (Q), and the self-resonant frequency (f/sub SR/) can be determined by its series inductance, equivalent capacitance, and series resistance. In this paper, the distributed capacitance models have been developed to predict the equivalent capacitances of the on-chip spiral inductors such as planar and stacked inductor. Based on the equivalent capacitances formulas, a simple accurate methodology is proposed to build a compact model to predict the behaviors of on-chip inductors. A large amount of inductors have been implemented in 0.25-/spl mu/m and 0.35-/spl mu/m CMOS processes to demonstrate the prediction accuracy.

This paper describes a 3.3 V-110 MHz 10 bit CMOS current-mode digital to analog converter (DAC) weighting with a 6 MSB current matrix stage and a 4 LSB binary weighting stage. The linearity errors (INL/DNL) caused by random and system errors are reduced by the proposed 2D hierarchically symmetrical centroid sequencing methodology. A new deglitch circuit is proposed to minimize the glitch energy. The simulation shows a conversion rate of 110 MHz, INI/DNL of /spl plusmn/0.8 LSB//spl plusmn/0.5 LSB, a glitch energy of 3.5 pV/spl middot/sec, and a power dissipation of 126 mW at 3.3 V.

In this paper, an efficient VLSI architecture to compute the n-bit Montgomery modular multiplication is proposed. By using the staged carry save adder (CSA) array, the computation cycles of addition reduced by about 3n/8. In addition, we apply the switch unit to save 2Q-2 registers from the traditional Q-bit CSA. Compare with the original method, the total clock cycles can be reduced by 68% in the case of n=1024 and Q=512 bits.