Proceedings. IEEE Asia-Pacific Conference on ASIC,
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A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large are......
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
Design of a DMT-based baseband transceiver for very-high-speed digital subscriber lines
- Trang 367-370
In this paper, we propose a transceiver design for the ETSI VDSL standard that uses the discrete multi-tone (DMT) modulation. Algorithms for channel estimation/equalization, symbol synchronization, sampling clock tracking are designed and integrated into the receiver architecture. Fixed-point simulation of the whole system shows that the proposed receiver architecture is capable of very high-rate ......
#Baseband #Transceivers #DSL #Telecommunication standards #OFDM modulation #Channel estimation #Synchronization #Sampling methods #Clocks #Algorithm design and analysis
Power efficient MPEG-4 decoder architecture featuring low-complexity error resilience
- Trang 225-228
A media processor supporting MPEG-4 SP@LI and H.263 baseline has been developed. This processor includes a RISC core, dedicated video decoding hardware, audio/voice decoder, post processor, and some peripherals. In order to increase flexibility and reduce power dissipation, separated bus architecture, which may minimize the bus transaction, is adopted. An enhanced error resiliency is also equipped......
#MPEG 4 Standard #Decoding #Resilience #Coprocessors #Energy consumption #Reduced instruction set computing #Codecs #Clocks #Process control #SDRAM
The CMOS on-chip oscillator based on level tracking technique
- Trang 197-200
In this paper, we propose the architecture of a CMOS fully integrated level-locked loop (LLL). A 455 kHz LLL without external reference signal achieves the target of 1 percent variation, and consumes 9 mW with 3.6 V power supply in a standard 0.5 /spl mu/m CMOS process. The frequency-to-voltage converter (FVC) in the LLL, built upon the charge redistribution principle, can decrease the process var......
#Power supplies #Voltage-controlled oscillators #Target tracking #Signal processing #CMOS process #Frequency conversion #Programmable control #Delay effects #Circuit noise #Regulators
A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique
- Trang 181-184
A CMOS comparator operating over a 1 V to 5 V supply range is presented. No special low-voltage technology is used for fabrication. An experimental chip was fabricated using a 0.5 /spl mu/m 5 V CMOS double-poly double-metal technology. The chip area of the comparator was 230/spl times/160 /spl mu/m/sup 2/. Measured results at 1 V supply voltage show a comparator response time of less than 4 /spl m......
#Preamplifiers #Sampling methods #Parasitic capacitance #Switches #CMOS technology #Low voltage #Energy consumption #Capacitors #Semiconductor device measurement #Time measurement
Design and implementation of an acoustic echo canceller
- Trang 299-302
In this paper the AEC (acoustic echo canceller) is designed and implemented using VHDL. The designed echo canceller employs a pipeline and master-slave structure, and is realized with FPGA. As an adaptive algorithm, the normalized LMS algorithm is used. For coefficient adjustment, the stochastic iteration algorithm (SIA) which uses only current residual values is used and the number of registers a......
#Echo cancellers #Field programmable gate arrays #Pipelines #Master-slave #Adaptive algorithm #Least squares approximation #Stochastic processes #Convergence #Finite impulse response filter #Transceivers
A high performance class AB CMOS rail to rail voltage follower
- Trang 161-163
A high performance class AB CMOS rail to rail voltage follower is presented. The circuit is based on the symmetrical class AB voltage follower and can operate under supply voltages of /spl plusmn/1.5 V. The proposed circuit has power dissipation of 2.5 mW under quiescent condition and can drive /spl plusmn/1.2 V to 250 /spl Omega/ load with a total harmonic distortion of less than 0.6 percent and ......
#Voltage #Power dissipation #MOSFETs #CMOS technology #Impedance #Drives #Harmonic distortion #Circuit stability #Joining processes #MOS devices
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
- Trang 359-362
This paper presents the VLSI design of a reconfigurable multimode Reed Solomon (RS) codec for various high-speed communication systems. Our decoder design is based on the Euclidean algorithm such that the datapath units are regular and simple. With its ability to support a variety of (n, k, t) RS specifications (0/spl les/t/spl les/8) and (0/spl les/n/spl les/255), this RS codec design is suitable......
#Very large scale integration #Reed-Solomon codes #Codecs #CMOS technology #Decoding #Algorithm design and analysis #Modems #Clocks #Frequency #Data processing
A direct-conversion CMOS receiver for 5 GHz wireless LAN
- Trang 311-314
This paper presents a direct conversion fully integrated receiver for 5 GHz wireless LAN fabricated in a 0.18 /spl mu/m CMOS technology. It combines low-noise amplifier, mixer, integer-N frequency synthesizer, automatic gain control, low pass channel-select filter, and analog-to-digital converter. The cascade noise figure is 8 dB, and the cascade IIP3 is -7.05 dBm. In active mode, the receiver dra......
#Wireless LAN #Low pass filters #Noise figure #Signal to noise ratio #Voltage-controlled oscillators #Low-noise amplifiers #Mixers #Frequency synthesizers #Gain control #Costs
A new 4-phase charge pump without body effects for low supply voltages
- Trang 53-56
A new four-phase charge pumping circuit for low supply voltages using 0.6 /spl mu/m triple-well CMOS technology to generate high negative boosted voltages is presented. With the new substrate connected technique, the influence of threshold voltage (-0.94 V) is minimized and the body effect is almost eliminated. A five-stage charge pump can efficiently pump lower than -7 V at supply voltage of 1.8 ......
#Charge pumps #Low voltage #MOSFETs #Circuits #Threshold voltage #Clocks #CMOS technology #Degradation #Flash memory #Diodes