Proceedings. IEEE Asia-Pacific Conference on ASIC,
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A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large are......
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
2002 IEEE Asia-Pacific Conference on ASIC. Proceedings (Cat. No.02EX547)
- 2002
Presents the front cover of the proceedings record.
Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture
- Trang 209-212
The traditional debug tools for chip tests and software developments need huge investment and plenty of time. These problems can be overcome by an embedded debugger based the JTAG boundary scan architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for testability problems. We designed the RED (reusable embedded debugger) using the JTAG boundary scan architecture. The proposed d......
#Reduced instruction set computing #Computer architecture #Software debugging #Ice #Circuits #Protocols #Software testing #Hardware #Costs #Investments
Spread-spectrum clocking in switching regulators to reduce EMI
- Trang 141-144
This paper describes a simple, inexpensive technique for intentionally broadening and flattening the spectrum of a DC-DC converter (switching regulator) to reduce electromagnetic interference (EMI). This noise spectrum broadening technique involves intentionally introducing pseudorandom dithering of control clock timing, which can be achieved by adding simple digital circuitry. This technique can ......
#Spread spectrum communication #Clocks #Regulators #Electromagnetic interference #Circuit noise #DC-DC power converters #Noise reduction #Circuit testing #Switching converters #Timing
An exact algorithm for practical routing problems
- Trang 343-346
In this paper, we propose an exact algorithm for practical routing problems in automated cell generation. We assume grid-based, Manhattan two layer model. Experimental results show that the proposed method can generate better solutions than commercial tools with respect to the wire length and the number of vias. Our algorithm takes account of the characteristics of VLSI layouts, such as silicides ......
#Routing #Silicides #Very large scale integration #Mesh generation #Application specific integrated circuits #Design methodology #Cost function #Terminology
Design of a DMT-based baseband transceiver for very-high-speed digital subscriber lines
- Trang 367-370
In this paper, we propose a transceiver design for the ETSI VDSL standard that uses the discrete multi-tone (DMT) modulation. Algorithms for channel estimation/equalization, symbol synchronization, sampling clock tracking are designed and integrated into the receiver architecture. Fixed-point simulation of the whole system shows that the proposed receiver architecture is capable of very high-rate ......
#Baseband #Transceivers #DSL #Telecommunication standards #OFDM modulation #Channel estimation #Synchronization #Sampling methods #Clocks #Algorithm design and analysis
A new 4-phase charge pump without body effects for low supply voltages
- Trang 53-56
A new four-phase charge pumping circuit for low supply voltages using 0.6 /spl mu/m triple-well CMOS technology to generate high negative boosted voltages is presented. With the new substrate connected technique, the influence of threshold voltage (-0.94 V) is minimized and the body effect is almost eliminated. A five-stage charge pump can efficiently pump lower than -7 V at supply voltage of 1.8 ......
#Charge pumps #Low voltage #MOSFETs #Circuits #Threshold voltage #Clocks #CMOS technology #Degradation #Flash memory #Diodes
A novel self-repairable parallel multiplier architecture, design and test
- Trang 29-32
A novel, self-repairable, parallel multiplier architecture with high speed low power CMOS parallel counter circuits and design-for-test (DFT) implementations is presented. The illustrated 16/spl times/16-b multiplier architecture can be easily reconfigured into 17 different architectures for fault recovering. Also described is a novel verification scheme that performs exhaustive data validation. C......
#Automatic testing #Circuit testing #Circuit faults #Adders #Computer architecture #Concurrent computing #Power engineering computing #Design engineering #Power engineering and energy #Power system reliability
A programmable data background generator for march based memory testing
- Trang 347-350
Due to the short test time and high fault coverage, march algorithms have been widely used to test the SRAM and DRAM memory chips and cores in a system-on-chip (SOC). To raise the fault coverage of the word-oriented memories (WOMs), distinct data backgrounds of the march algorithms are required. In this paper we have integrated two kinds of data background generators into a single design in the bu......
#Circuit faults #System testing #Hardware #Random access memory #System-on-a-chip #Built-in self-test #Circuit testing #Combinational circuits #Costs
Self-isolated gain-enhanced sense amplifier
- Trang 57-60
The work describes a self-isolated gain-enhanced sense amplifier (SGSA) for high-speed memory. A pair of incoming signals with large capacitive load can be self-isolated to the input nodes of the SGSA during the transient operation. The input nodes of the SGSA are then regenerated through the self-feedback control of the sense amplifier. Thus the gain is enhanced and the speed and driving capabili......
#Random access memory #Logic circuits #Feedback #Differential amplifiers #Very large scale integration #High speed integrated circuits #Laboratories #Operational amplifiers #Signal design #Integrated circuit interconnections