Proceedings. IEEE Asia-Pacific Conference on ASIC,
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Các bài báo tiêu biểu
A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large are......
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
Explicit transfer function of RC polyphase filter for wireless transceiver analog front-end
- Trang 137-140
This paper derives explicit frequency transfer functions for first-, second- and third-order RC polyphase filters (which are important components in analog front-end of wireless transceivers for I, Q signal generation and image rejection) using a concept of complex signal and circulant matrix properties. The results allow us to exploit their characteristics systematically.
#Transfer functions #Filters #Transceivers #Image generation #Signal generators #RF signals #Radio frequency #Circuits #Analytical models #Fourier transforms
Spread-spectrum clocking in switching regulators to reduce EMI
- Trang 141-144
This paper describes a simple, inexpensive technique for intentionally broadening and flattening the spectrum of a DC-DC converter (switching regulator) to reduce electromagnetic interference (EMI). This noise spectrum broadening technique involves intentionally introducing pseudorandom dithering of control clock timing, which can be achieved by adding simple digital circuitry. This technique can ......
#Spread spectrum communication #Clocks #Regulators #Electromagnetic interference #Circuit noise #DC-DC power converters #Noise reduction #Circuit testing #Switching converters #Timing
A 2.5 Gbps CMOS laser diode driver with preemphasis technique
- Trang 65-68
This paper describes the design of a 2.5 Gbps laser diode (LD) driver circuit in a 0.35/spl mu/m digital CMOS process. The LD driver delivers a biased current range from 5 to 10 mA and a modulation current of 20 mA. The biased current is programmable by a 3-bit D/A. High current driving capability as well as agile switching speed are achieved by inductive peaking and preemphasis techniques. Operat......
#Diode lasers #Driver circuits #High speed optical techniques #Optical modulation #Power control #Optical design #Stimulated emission #Threshold current #Preamplifiers #CMOS process
Tunable injection current compensation architecture for high fill-factor self-buffered active pixel sensor
- Trang 101-104
A high fill-factor self-buffered active pixel sensor and a tunable injection current compensation architecture for high dynamic range imager is proposed for scaled CMOS technology. The new cell, including a photodiode, is formed by n-well and p-type substrate and a single-transistor output buffer can achieve fill-factor of 55%. Dynamic range of up to 120 dB is projected by simulation results. Expe......
#CMOS image sensors #Diodes #Voltage #Tunable circuits and devices #Dynamic range #CMOS technology #Pixel #Circuit simulation #Costs #Equivalent circuits
Automatic Verilog code generation of an 8-bit RISC micro-controller
- Trang 327-330
In this paper, we describe a design method, which can automatically generate Verilog code for an 8-bit RISC microcontroller with a user-defined instruction set. With this method, one can shorten the development time, increase the efficiency of Verilog coding, and decrease the man-hour requirement. Most of all, even those who do not have the knowledge and techniques of a Verilog coding for a RISC m......
#Hardware design languages #Reduced instruction set computing #Design methodology #Databases #Automatic control #Pipelines #Decoding #Algorithms #Automatic generation control #Debugging
A 4-KB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline drivers and high-V/sub THP/ latches
- Trang 49-52
The design of a prototypical 500-MHz CMOS 4-T SRAM is presented. The storage of data is realized by a pair of cross-coupled PMOS transistors, while the wordline controls a pair of NMOS transistors. The wordline voltage compensation circuit and bitline boosting circuit, then, are neither needed to enhance the data retention of memory cells. Built-in self-refreshing paths makes the data retention po......
#Random access memory #Propagation delay #National electric code #Voltage #Detectors #Driver circuits #Leakage current #Threshold current #Subthreshold current #Equations
A programmable data background generator for march based memory testing
- Trang 347-350
Due to the short test time and high fault coverage, march algorithms have been widely used to test the SRAM and DRAM memory chips and cores in a system-on-chip (SOC). To raise the fault coverage of the word-oriented memories (WOMs), distinct data backgrounds of the march algorithms are required. In this paper we have integrated two kinds of data background generators into a single design in the bu......
#Circuit faults #System testing #Hardware #Random access memory #System-on-a-chip #Built-in self-test #Circuit testing #Combinational circuits #Costs
Transfer function design of stable high-order sigma-delta modulators with root locus inside unit circle
- Trang 5-8
In this paper, a systematic method to design stable high-order sigma-delta modulator (SDM) transfer functions, with no need of stability mechanisms, is proposed. It is shown that a high-order SDM can be absolutely stable if the departure angles of the root locus of its noise-shaping function are properly designed. Tradeoffs between stability and performance of the SDMs are presented.
#Transfer functions #Delta-sigma modulation #H infinity control #Gain #Noise shaping #Cities and towns #Stability analysis #Ear #Linear systems #Signal to noise ratio
A 5.5 GHz prescaler in 0.18 /spl mu/m CMOS technology
- Trang 69-72
A high-speed dual-modulus divide-by-32/33 prescaler (DMP) has been fabricated in a standard 0.18 /spl mu/m CMOS process. It consists of a divide-by-4/5 synchronous divider implemented in MOS current-mode logic and a divide-by-8 asynchronous counter realized in differential cascode voltage-switch logic. A fully differential architecture is adopted, which offers immunity against noise, fabrication p......
#CMOS technology #CMOS logic circuits #Voltage #CMOS process #Counting circuits #Circuit noise #Fabrication #Frequency measurement #Wireless LAN #Power supplies