Proceedings. IEEE Asia-Pacific Conference on ASIC,
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A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large are...... hiện toàn bộ
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
Design and implementation of an acoustic echo canceller
- Trang 299-302
In this paper the AEC (acoustic echo canceller) is designed and implemented using VHDL. The designed echo canceller employs a pipeline and master-slave structure, and is realized with FPGA. As an adaptive algorithm, the normalized LMS algorithm is used. For coefficient adjustment, the stochastic iteration algorithm (SIA) which uses only current residual values is used and the number of registers a...... hiện toàn bộ
#Echo cancellers #Field programmable gate arrays #Pipelines #Master-slave #Adaptive algorithm #Least squares approximation #Stochastic processes #Convergence #Finite impulse response filter #Transceivers
An exact algorithm for practical routing problems
- Trang 343-346
In this paper, we propose an exact algorithm for practical routing problems in automated cell generation. We assume grid-based, Manhattan two layer model. Experimental results show that the proposed method can generate better solutions than commercial tools with respect to the wire length and the number of vias. Our algorithm takes account of the characteristics of VLSI layouts, such as silicides ...... hiện toàn bộ
#Routing #Silicides #Very large scale integration #Mesh generation #Application specific integrated circuits #Design methodology #Cost function #Terminology
A novel block equalization design for wireless communication with ISI and Rayleigh fading channels
- Trang 291-294
In this paper, a novel block channel equalization design for wireless communication over mobile radio channels with both inter-symbol interference (ISI) and Rayleigh fading is presented. The proposed design consists of a matched filter, a channel estimator and a block decision feedback equalizer (BDFE). The channel estimator, which is based on a revised RLS algorithm, adopts a semi-blind approach....... hiện toàn bộ
#Wireless communication #Intersymbol interference #Fading #Rayleigh channels #Matched filters #Detectors #Land mobile radio #Decision feedback equalizers #Resonance light scattering #Filtering
Memory synthesis for low power ASIC design
- Trang 335-342
In this paper we describe a multi-module, multiport memory design procedure that satisfies area and/or energy constraints. Our procedure consists of using ILP models and heuristic-based algorithms to determine (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy cons...... hiện toàn bộ
#Application specific integrated circuits #Energy consumption #Heuristic algorithms #Costs #Electrocardiography #Very large scale integration #Focusing #Multidimensional systems #Streaming media #Video sequences
A new low-voltage CMOS 1-bit full adder for high performance applications
- Trang 21-24
In this paper, a new low-voltage high-performance CMOS 1-bit full adder circuit is proposed. The new design is derived by combining XOR (XNOR) gates, used in the conventional full adder, and transmission gates. The proposed full adder can provide full voltage swing at a low supply voltage and offers superior performance in both power and speed than the conventional full adder, the transmission ful...... hiện toàn bộ
#Adders #Low voltage #Very large scale integration #Power supplies #Power dissipation #CMOS technology #Digital signal processing #Batteries #Circuit synthesis #Energy consumption
A high-throughput low-cost AES cipher chip
- Trang 85-88
We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 /spl mu/m CMOS technology, a 200 MHz clock i...... hiện toàn bộ
#Elliptic curve cryptography #Hardware #CMOS technology #Clocks #Application specific integrated circuits #Table lookup #Laboratories #Costs #Internet #Communication system security
A low-distortion and swing-suppression sigma-delta modulator with extended dynamic range
- Trang 9-12
This work presents a novel low-distortion and swing-suppression second-order sigma-delta modulator with extended dynamic range. The proposed modulator is based on the dual-quantizer architecture and can effectively extend dynamic range by only adding two simple digital filters in the digital circuit. The technique for low-distortion and swing-suppression of the modulator are also proposed. Accordi...... hiện toàn bộ
#Delta-sigma modulation #Dynamic range #Circuit topology #Wideband #Transfer functions #Bandwidth #Analog circuits #Quantization #Very large scale integration #Frequency
A high performance class AB CMOS rail to rail voltage follower
- Trang 161-163
A high performance class AB CMOS rail to rail voltage follower is presented. The circuit is based on the symmetrical class AB voltage follower and can operate under supply voltages of /spl plusmn/1.5 V. The proposed circuit has power dissipation of 2.5 mW under quiescent condition and can drive /spl plusmn/1.2 V to 250 /spl Omega/ load with a total harmonic distortion of less than 0.6 percent and ...... hiện toàn bộ
#Voltage #Power dissipation #MOSFETs #CMOS technology #Impedance #Drives #Harmonic distortion #Circuit stability #Joining processes #MOS devices
A VLSI architecture of DMT based transceiver for VDSL system
- Trang 363-366
This paper presents a VLSI architecture of the transceiver for DMT-VDSL system with data rate as high as 52 Mbps. Consisting of four radix-2 stages and three radix2/4/8 stages, a variable length pipelined architecture of FFT/IFFT compatible with 5 modes is proposed to perform the DMT modulation/demodulation. Based on LMS adaptation algorithm, time domain equalizer (TEQ) and frequency domain equali...... hiện toàn bộ
#Very large scale integration #OFDM modulation #Transceivers #Crosstalk #DSL #Radiofrequency interference #Radio broadcasting #Transmitters #Data engineering #Least squares approximation