Proceedings. IEEE Asia-Pacific Conference on ASIC,
Cơ quản chủ quản: N/A
Các bài báo tiêu biểu
A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large are......
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
A new 4-phase charge pump without body effects for low supply voltages
- Trang 53-56
A new four-phase charge pumping circuit for low supply voltages using 0.6 /spl mu/m triple-well CMOS technology to generate high negative boosted voltages is presented. With the new substrate connected technique, the influence of threshold voltage (-0.94 V) is minimized and the body effect is almost eliminated. A five-stage charge pump can efficiently pump lower than -7 V at supply voltage of 1.8 ......
#Charge pumps #Low voltage #MOSFETs #Circuits #Threshold voltage #Clocks #CMOS technology #Degradation #Flash memory #Diodes
A high performance class AB CMOS rail to rail voltage follower
- Trang 161-163
A high performance class AB CMOS rail to rail voltage follower is presented. The circuit is based on the symmetrical class AB voltage follower and can operate under supply voltages of /spl plusmn/1.5 V. The proposed circuit has power dissipation of 2.5 mW under quiescent condition and can drive /spl plusmn/1.2 V to 250 /spl Omega/ load with a total harmonic distortion of less than 0.6 percent and ......
#Voltage #Power dissipation #MOSFETs #CMOS technology #Impedance #Drives #Harmonic distortion #Circuit stability #Joining processes #MOS devices
An 8-way VLIW embedded multimedia processor with advanced cache mechanism
- Trang 213-216
An 8-way VLIW embedded multimedia processor is developed in 0.11 /spl mu/m 7-layer Cu/Al metal CMOS process technology. The processor achieved the peak performance of 2132 MIPS/2.1 GFLOPS/4.26 GOPS at 533 MHz. This processor equips 4-way integer and 4-way floating/media pipelines. Each media pipeline can execute a 4-parallel SIMD instruction, so 16-operations can be executed at a cycle. It also eq......
#VLIW #Pipelines #Laboratories #Energy consumption #CMOS process #Decoding #Microprocessors #Circuits #CMOS technology #Process design
A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture
- Trang 1-4
In this paper, a very low-voltage fourth-order bandpass delta-sigma modulator with a two-path architecture is presented. Using the modified switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without any voltage multiplier or bootstrapping switch. Realized in a 0.25 /spl mu/m 1P5M standard CMOS process, the prototype modulator exhibits a signal-to-noise-plus-dist......
#Delta modulation #Low voltage #Clocks #Transfer functions #Switching circuits #Voltage control #Band pass filters #Signal processing #Feedback circuits #Sampling methods
Analog circuit for sound localization applications
- Trang 17-20
We describe an analog CMOS circuit that computes the time (phase) delay between two 10 kHz sinusoids. This circuit can be used in sound localization applications. We realize a locking range of 10 - 170 degrees in less than 1 ms that is robust over process variations. Two receivers placed at a distance from one another intercept a sinusoidal waveform emanating from a sound source. The phase differe......
#Analog circuits #CMOS analog integrated circuits #Analog computers #Delay effects #Robustness #Signal detection #Phase detection #Phase estimation #Digital signal processing #Hardware
Delay-difference DLL and its-application on skewed output buffer
- Trang 279-282
The delay-locked loop (DLL) is the key element to reduce clock skew, and provide multiple clock phases. In this paper, a DLL based upon self-biased techniques is designed. Then an improved 2D array DLL is proposed, based on the 1D DLL. Also, a new 3D DLL structure is proposed. The DLL is fabricated with 2 V 0.35 /spl mu/m CMOS technology, and the measurement results shows that the peak to peak jit......
#Delay #Clocks #CMOS technology #Phased arrays #Jitter #Voltage #Frequency #Noise reduction #Inductance #Fluctuations
A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique
- Trang 181-184
A CMOS comparator operating over a 1 V to 5 V supply range is presented. No special low-voltage technology is used for fabrication. An experimental chip was fabricated using a 0.5 /spl mu/m 5 V CMOS double-poly double-metal technology. The chip area of the comparator was 230/spl times/160 /spl mu/m/sup 2/. Measured results at 1 V supply voltage show a comparator response time of less than 4 /spl m......
#Preamplifiers #Sampling methods #Parasitic capacitance #Switches #CMOS technology #Low voltage #Energy consumption #Capacitors #Semiconductor device measurement #Time measurement
2.5 Gbps CMOS laser diode driver with APC and digitally controlled current modulation
- Trang 77-80
This laser diode driver operates at 2.5 Gbps. It contains a driver, a reference voltage generator, an automatic power control circuit and digitally controlled blocks of bias current and modulation current. The TSMC 0.35 /spl mu/m 1P4M CMOS digital process is used to fabricate this chip. APC is used to maintain the laser diode output power and it works when photodetector gain ranges from 1/80 to 1/......
#Diode lasers #Digital control #Optical control #Digital modulation #Driver circuits #Power generation #Automatic control #Power control #Automatic generation control #Automatic voltage control
Design of a DMT-based baseband transceiver for very-high-speed digital subscriber lines
- Trang 367-370
In this paper, we propose a transceiver design for the ETSI VDSL standard that uses the discrete multi-tone (DMT) modulation. Algorithms for channel estimation/equalization, symbol synchronization, sampling clock tracking are designed and integrated into the receiver architecture. Fixed-point simulation of the whole system shows that the proposed receiver architecture is capable of very high-rate ......
#Baseband #Transceivers #DSL #Telecommunication standards #OFDM modulation #Channel estimation #Synchronization #Sampling methods #Clocks #Algorithm design and analysis