Proceedings. IEEE Asia-Pacific Conference on ASIC,
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Các bài báo tiêu biểu
A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip
area. Q (quality factor) of the proposed filter can be mostly determined by the
ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of
the values of two capacitance similar to the conventional band-pass filter.
Therefore, the proposed filter does not need large capacitance that occupies
large are...
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
A low power CMOS adaptive line equalizer for fast Ethernet
- Trang 129-132
An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet
data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed
adaptive equalizer is designed for the 0.35 /spl mu/m CMOS process. The designed
equalizer has low power consumption (19 mW) and small silicon area (0.07 mm/sup
2/).
#Ethernet networks #Communication cables #Bandwidth #Filters #Transfer functions #Frequency #Adaptive equalizers #Poles and zeros #Circuits #Data communication
A 3.3 V-110 MHz 10-bit CMOS current-mode DAC
- Trang 173-176
This paper describes a 3.3 V-110 MHz 10 bit CMOS current-mode digital to analog
converter (DAC) weighting with a 6 MSB current matrix stage and a 4 LSB binary
weighting stage. The linearity errors (INL/DNL) caused by random and system
errors are reduced by the proposed 2D hierarchically symmetrical centroid
sequencing methodology. A new deglitch circuit is proposed to minimize the
glitch energy. T...
#Symmetric matrices #Linearity #Matrix converters #Circuit simulation #Transconductance #CMOS technology #Power engineering and energy #Impedance #Analog-digital conversion #Power dissipation
A 0.18-/spl mu/m CMOS offset-PLL upconversion modulation loop IC for DCS-1800 transmitter
- Trang 307-310
A DCS-1800 offset-PLL upconversion modulation loop IC, which is fabricated in a
0.18-/spl mu/m CMOS technology, is presented in this paper. This IC operates at
2.8 V supply voltage with a current consumption of 36 mA. The measured r.m.s.
and peak phase errors of the GMSK transmission signal are 1.6 and 4 degree,
respectively. It is shown that such circuit can be implemented in a CMOS process
with ...
#CMOS integrated circuits #Transmitters #Voltage-controlled oscillators #Phase frequency detector #CMOS technology #CMOS process #Transceivers #BiCMOS integrated circuits #Radio frequency #Phase modulation
A low power, wide operating frequency and high noise immunity half-digital phased-locked loop
- Trang 263-266
In this paper, a low power, wide operating frequency and high noise immunity
half-digital phase locked loop (HDPLL) is proposed and analyzed. A novel
voltage-controlled oscillator (VCO) is proposed and used to improve linear V-f
characteristic and reduce the total power consumption for the HDPLL design. By
HSPICE simulation results, the power dissipation of the novel VCO can be reduced
over 50% in...
#Frequency #Phase noise #Voltage-controlled oscillators #Phase locked loops #Power dissipation #Circuit noise #Voltage control #Jitter #Phase detection #Filters
Self-isolated gain-enhanced sense amplifier
- Trang 57-60
The work describes a self-isolated gain-enhanced sense amplifier (SGSA) for
high-speed memory. A pair of incoming signals with large capacitive load can be
self-isolated to the input nodes of the SGSA during the transient operation. The
input nodes of the SGSA are then regenerated through the self-feedback control
of the sense amplifier. Thus the gain is enhanced and the speed and driving
capabili...
#Random access memory #Logic circuits #Feedback #Differential amplifiers #Very large scale integration #High speed integrated circuits #Laboratories #Operational amplifiers #Signal design #Integrated circuit interconnections
VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems
- Trang 359-362
This paper presents the VLSI design of a reconfigurable multimode Reed Solomon
(RS) codec for various high-speed communication systems. Our decoder design is
based on the Euclidean algorithm such that the datapath units are regular and
simple. With its ability to support a variety of (n, k, t) RS specifications
(0/spl les/t/spl les/8) and (0/spl les/n/spl les/255), this RS codec design is
suitable...
#Very large scale integration #Reed-Solomon codes #Codecs #CMOS technology #Decoding #Algorithm design and analysis #Modems #Clocks #Frequency #Data processing
High-speed low-complexity implementation for data weighted averaging algorithm [/spl Sigma//spl Delta/ modulator applications]
- Trang 283-286
In this paper, a high-speed, low-complexity implementation of a data weighted
averaging (DWA) algorithm is presented. Different from other published
implementations, the maximum speed-limited function of the DWA algorithm,
decoding for control signal generation and adding for register value updating,
are replaced by carry look-ahead and rotating. Additionally, register
simplification is adopted to...
#Cities and towns #Decoding #Costs #Delta-sigma modulation #Logic #Circuits #Physics #Data engineering #DH-HEMTs #Signal generators
A new floating-point normalization scheme by bit parallel operation of leading one position value
- Trang 221-224
In this paper, a new normalization design method for a floating-point unit is
presented. Shift amount information for normalization is devised to generate
leading one position value (LOPV). LOPV is the number with all zero bits except
the leading one position. LOPV can be easily generated by two NOR planes, which
implies it can be implemented by bit-parallel operations. Therefore, LOPV can be
acqu...
#Decoding #Counting circuits #CMOS technology #Design methodology #Delay effects #Voltage #Area measurement #Semiconductor device measurement #Optimization methods #Signal generators
Fast and compact dynamic ripple carry adder design
- Trang 25-28
Adders are fundamental building blocks and often constitute part of the critical
path. In this paper, we propose four high-speed ripple carry adder designs using
dynamic circuit techniques. CMOS technology based SPICE simulations show that
the proposed dynamic ripple carry adders are at least two times faster than the
conventional static ripple carry adder. Further, all of the proposed designs
com...
#Adders #CMOS logic circuits #Logic design #Propagation delay #Switches #SPICE #Circuit simulation #Very large scale integration #Arithmetic #Voltage