Proceedings. IEEE Asia-Pacific Conference on ASIC,
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A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large are......
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
A high-throughput low-cost AES cipher chip
- Trang 85-88
We propose an efficient hardware implementation of the AES (Advanced Encryption Standard) algorithm, with key expansion capability. Compared with the widely used table-lookup technique, the proposed basis transformation technique reduces the hardware overhead of the S-box by 64%. Our pipelined design has a very high throughput rate. Using a typical 0.35 /spl mu/m CMOS technology, a 200 MHz clock i......
#Elliptic curve cryptography #Hardware #CMOS technology #Clocks #Application specific integrated circuits #Table lookup #Laboratories #Costs #Internet #Communication system security
Structure configuration of low power register file using energy model
- Trang 41-44
This paper presents a transistor-level energy model of register files that using multi-port SRAM technology. Some register file circuit techniques are compared in energy efficiencies with the architectural parameters. According to the calculating and comparison results of energy model, structure configuration of register file is discussed from the point view of energy-efficiency. The realization o......
#Registers #Circuits #Decoding #Semiconductor device modeling #Energy consumption #Switches #Energy efficiency #CMOS technology #Microprocessors #Energy dissipation
Author index
- Trang 375 - 2002
The author index contains an entry for each author and coauthor included in the proceedings record.
A low power CMOS adaptive line equalizer for fast Ethernet
- Trang 129-132
An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed adaptive equalizer is designed for the 0.35 /spl mu/m CMOS process. The designed equalizer has low power consumption (19 mW) and small silicon area (0.07 mm/sup 2/).
#Ethernet networks #Communication cables #Bandwidth #Filters #Transfer functions #Frequency #Adaptive equalizers #Poles and zeros #Circuits #Data communication
Analysis and design of CMOS broadband amplifier with dual feedback loops
- Trang 245-248
We present a broadband amplifier with 10.5dB gain and a 3dB bandwidth of 1.7GHz using CMOS 0.25/spl mu/m process in this paper. The technique of dual feedback loops was used in the amplifier for terminal impedance matching. Derived formulas for voltage gain (or S/sub 21/), input return loss(or S/sub 11/), output return loss (or S/sub 22/) as well as transimpedance gain with open load and 50 /spl O......
#Broadband amplifiers #Feedback loop #Voltage #Resistors #Bandwidth #CMOS technology #Optical amplifiers #Impedance matching #Feedback circuits #MOS devices
Explicit transfer function of RC polyphase filter for wireless transceiver analog front-end
- Trang 137-140
This paper derives explicit frequency transfer functions for first-, second- and third-order RC polyphase filters (which are important components in analog front-end of wireless transceivers for I, Q signal generation and image rejection) using a concept of complex signal and circulant matrix properties. The results allow us to exploit their characteristics systematically.
#Transfer functions #Filters #Transceivers #Image generation #Signal generators #RF signals #Radio frequency #Circuits #Analytical models #Fourier transforms
Automatic Verilog code generation of an 8-bit RISC micro-controller
- Trang 327-330
In this paper, we describe a design method, which can automatically generate Verilog code for an 8-bit RISC microcontroller with a user-defined instruction set. With this method, one can shorten the development time, increase the efficiency of Verilog coding, and decrease the man-hour requirement. Most of all, even those who do not have the knowledge and techniques of a Verilog coding for a RISC m......
#Hardware design languages #Reduced instruction set computing #Design methodology #Databases #Automatic control #Pipelines #Decoding #Algorithms #Automatic generation control #Debugging
A comma-free Reed-Solomon decoder chip for W-CDMA/FDD applications
- Trang 355-358
A (15, 3) CFRS (comma-free Reed-Solomon) code has been devised in the 3GPP W-CDMA/FDD system (3/sup rd/ generation partnership project, wideband code division multiple access/frequency division duplexing) in order to facilitate frame synchronization and code-group identification in the cell search procedure. This paper proposes a CFRS decoder chip for fast, multi-speed decoding in this application......
#Reed-Solomon codes #Decoding #Multiaccess communication #Synchronization #CMOS technology #Global Positioning System #Systolic arrays #Power dissipation #Clocks #Delay effects
Spread-spectrum clocking in switching regulators to reduce EMI
- Trang 141-144
This paper describes a simple, inexpensive technique for intentionally broadening and flattening the spectrum of a DC-DC converter (switching regulator) to reduce electromagnetic interference (EMI). This noise spectrum broadening technique involves intentionally introducing pseudorandom dithering of control clock timing, which can be achieved by adding simple digital circuitry. This technique can ......
#Spread spectrum communication #Clocks #Regulators #Electromagnetic interference #Circuit noise #DC-DC power converters #Noise reduction #Circuit testing #Switching converters #Timing