Proceedings. IEEE Asia-Pacific Conference on ASIC,
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Các bài báo tiêu biểu
A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip
area. Q (quality factor) of the proposed filter can be mostly determined by the
ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of
the values of two capacitance similar to the conventional band-pass filter.
Therefore, the proposed filter does not need large capacitance that occupies
large are...
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
A real-time lipreading LSI for word recognition
- Trang 303-306
In the paper, we present a real-time lip-reading LSI for recognizing spoken
words from lip movement. The LSI recognizes up to 8 words based on the hidden
Markov model (HMM). The LSI accepts the 256/spl times/256 8-bit gray-scale
images from a camera, and outputs the 3-bit symbol code of words for 43 images
(corresponding to 1.53 s). We present a lip-reading algorithm optimized for
hardware impleme...
#Large scale integration #Hidden Markov models #Image edge detection #Gray-scale #Cameras #Speech recognition #Humans #Vector quantization #Hardware design languages #Image recognition
A V-driver circuit for lowering power of sub-0.1/spl mu/m bus
- Trang 267-270
A bus driver circuit which reduces the power dissipation of interconnects is
described. The proposed V-driver prevents simultaneous signal transitions of
opposite direction. Simulated results show up to 42.2% power reduction for 65 nm
CMOS technology. A test chip was fabricated and measured. The results show a
10.7% power reduction at 100 MHz, 1.0 V operation.
#Driver circuits #Timing #Capacitance #Inverters #Wire #Mirrors #Circuit simulation #Shape #Recycling #Delay
A 39-46 GHz MMIC HBT triple-push VCO using cascode configuration
- Trang 61-64 - 2002
This paper reports the development of a Q-band (33-50 GHz) triple-push VCO using
GaAs heterojunction bipolar transistor (HBT) MMIC technology. The circuit adopts
cascode configuration of HBTs in order to increase the negative resistance at
high frequency and thus to obtain a higher oscillation frequency. Based on the
measured results, MMIC VCO achieves a tuning frequency range of 39 to 46 GHz.
#MMICs #Heterojunction bipolar transistors #Voltage-controlled oscillators #Frequency #Tuning #Gallium arsenide #Circuit optimization #Resistors #Inductors #Electrical resistance measurement
2002 IEEE Asia-Pacific Conference on ASIC. Proceedings (Cat. No.02EX547)
- 2002
Presents the front cover of the proceedings record.
System-level requirements of DC-DC converters for dynamic power supplies of power amplifiers
- Trang 149-152
The energy efficiency of battery-operated portable applications can be improved
by increasing the efficiency of power amplifiers (PAs). By dynamically changing
the supply voltage from the fixed battery supply using a DC-DC converter, the PA
can be operated with high efficiency during power back-off. This paper presents
the system level requirements for a buck converter and other blocks in a dynami...
#DC-DC power converters #Power supplies #Power amplifiers #Energy efficiency #Voltage #Batteries #Buck converters #Circuit simulation #Delay effects #Power system modeling
A VLSI architecture of DMT based transceiver for VDSL system
- Trang 363-366
This paper presents a VLSI architecture of the transceiver for DMT-VDSL system
with data rate as high as 52 Mbps. Consisting of four radix-2 stages and three
radix2/4/8 stages, a variable length pipelined architecture of FFT/IFFT
compatible with 5 modes is proposed to perform the DMT modulation/demodulation.
Based on LMS adaptation algorithm, time domain equalizer (TEQ) and frequency
domain equali...
#Very large scale integration #OFDM modulation #Transceivers #Crosstalk #DSL #Radiofrequency interference #Radio broadcasting #Transmitters #Data engineering #Least squares approximation
A high performance function generator for multiplier-based arithmetic operations
- Trang 331-334
An automatic hardware generator is developed for computing multiplier-based
arithmetic functions. The generator can produce Verilog codes of parallel
multipliers/multiplier-accumulator/inner product calculator and their
corresponding test fixture files for pre-layout simulation. The irregular
connection of the Wallace tree in the parallel multiplier is optimized in order
to reduce the critical pat...
#Signal generators #Arithmetic #Hardware design languages #Testing #Fixtures #Computational modeling #Delay #Counting circuits #Libraries #Logic design
0.9-V sense-amplifier-based reduced-clock-swing MTCMOS flip-flops
- Trang 271-274
Scaling-down V/sub DD/ as well as adopting a reduced-swing clock simultaneously
is the key technique proposed in this work which results in remarkable power
reduction for VLSI chips. Several configurations of 0.9-V MTCMOS
(multi-threshold CMOS) flip-flops with reduced clock-swing (RCSFFs) are
investigated in this work. By using the MVT technique, and the pulsed-low
reduced-swing clock, the perform...
#Flip-flops #Clocks #Energy consumption #Threshold voltage #MOS devices #CMOS technology #Wires #Pulse circuits #Master-slave #Latches
Bộ phát DS-CDMA kỹ thuật số hoàn toàn và thiết kế VLSI cơ sở của bộ thu đầu cuối cho mạng cáp đầu lên Dịch bởi AI
- Trang 371-374
Bài báo này trình bày một bộ phát DS-CDMA hoàn toàn kỹ thuật số cho đường lên và
một bộ thu cơ sở đầu cuối cho các mạng cáp/HFC. Bộ phát đường lên hỗ trợ tính
linh hoạt tần số của sóng mang, các chòm sao QPSK và QAM lên đến 64QAM, tốc độ
ký hiệu biến đổi từ 160kchip/s đến 5.12Mchip/s, tăng gấp đôi theo lũy thừa, và
chuyển đổi lên số trực tiếp để đạt được độ chính xác trong biên độ và pha điều
chế....
#Giao tiếp đa truy cập #Bộ phát #Cơ sở #Tích hợp quy mô rất lớn #Bộ lọc #Thời gian #Tần số #Điều chế biên độ vuông #Cáp quang lai đồng trục #Khóa pha điều chế điều chế biên độ vuông