Proceedings. IEEE Asia-Pacific Conference on ASIC,
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A CMOS current-mode band-pass filter with small chip area
- Trang 13-16
In this paper, we propose a CMOS current-mode band-pass filter with small chip area. Q (quality factor) of the proposed filter can be mostly determined by the ratio of the MOSFET transconductances in a Q-setting part, not by the ratio of the values of two capacitance similar to the conventional band-pass filter. Therefore, the proposed filter does not need large capacitance that occupies large are...... hiện toàn bộ
#Band pass filters #Circuits #Passband #Q factor #Capacitors #Parasitic capacitance #CMOS technology #Permission #Transfer functions #Transconductance
Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture
- Trang 209-212
The traditional debug tools for chip tests and software developments need huge investment and plenty of time. These problems can be overcome by an embedded debugger based the JTAG boundary scan architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for testability problems. We designed the RED (reusable embedded debugger) using the JTAG boundary scan architecture. The proposed d...... hiện toàn bộ
#Reduced instruction set computing #Computer architecture #Software debugging #Ice #Circuits #Protocols #Software testing #Hardware #Costs #Investments
A low-distortion and swing-suppression sigma-delta modulator with extended dynamic range
- Trang 9-12
This work presents a novel low-distortion and swing-suppression second-order sigma-delta modulator with extended dynamic range. The proposed modulator is based on the dual-quantizer architecture and can effectively extend dynamic range by only adding two simple digital filters in the digital circuit. The technique for low-distortion and swing-suppression of the modulator are also proposed. Accordi...... hiện toàn bộ
#Delta-sigma modulation #Dynamic range #Circuit topology #Wideband #Transfer functions #Bandwidth #Analog circuits #Quantization #Very large scale integration #Frequency
Self-isolated gain-enhanced sense amplifier
- Trang 57-60
The work describes a self-isolated gain-enhanced sense amplifier (SGSA) for high-speed memory. A pair of incoming signals with large capacitive load can be self-isolated to the input nodes of the SGSA during the transient operation. The input nodes of the SGSA are then regenerated through the self-feedback control of the sense amplifier. Thus the gain is enhanced and the speed and driving capabili...... hiện toàn bộ
#Random access memory #Logic circuits #Feedback #Differential amplifiers #Very large scale integration #High speed integrated circuits #Laboratories #Operational amplifiers #Signal design #Integrated circuit interconnections
Delay-difference DLL and its-application on skewed output buffer
- Trang 279-282
The delay-locked loop (DLL) is the key element to reduce clock skew, and provide multiple clock phases. In this paper, a DLL based upon self-biased techniques is designed. Then an improved 2D array DLL is proposed, based on the 1D DLL. Also, a new 3D DLL structure is proposed. The DLL is fabricated with 2 V 0.35 /spl mu/m CMOS technology, and the measurement results shows that the peak to peak jit...... hiện toàn bộ
#Delay #Clocks #CMOS technology #Phased arrays #Jitter #Voltage #Frequency #Noise reduction #Inductance #Fluctuations
A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique
- Trang 181-184
A CMOS comparator operating over a 1 V to 5 V supply range is presented. No special low-voltage technology is used for fabrication. An experimental chip was fabricated using a 0.5 /spl mu/m 5 V CMOS double-poly double-metal technology. The chip area of the comparator was 230/spl times/160 /spl mu/m/sup 2/. Measured results at 1 V supply voltage show a comparator response time of less than 4 /spl m...... hiện toàn bộ
#Preamplifiers #Sampling methods #Parasitic capacitance #Switches #CMOS technology #Low voltage #Energy consumption #Capacitors #Semiconductor device measurement #Time measurement
Design and implementation of an acoustic echo canceller
- Trang 299-302
In this paper the AEC (acoustic echo canceller) is designed and implemented using VHDL. The designed echo canceller employs a pipeline and master-slave structure, and is realized with FPGA. As an adaptive algorithm, the normalized LMS algorithm is used. For coefficient adjustment, the stochastic iteration algorithm (SIA) which uses only current residual values is used and the number of registers a...... hiện toàn bộ
#Echo cancellers #Field programmable gate arrays #Pipelines #Master-slave #Adaptive algorithm #Least squares approximation #Stochastic processes #Convergence #Finite impulse response filter #Transceivers
A novel block equalization design for wireless communication with ISI and Rayleigh fading channels
- Trang 291-294
In this paper, a novel block channel equalization design for wireless communication over mobile radio channels with both inter-symbol interference (ISI) and Rayleigh fading is presented. The proposed design consists of a matched filter, a channel estimator and a block decision feedback equalizer (BDFE). The channel estimator, which is based on a revised RLS algorithm, adopts a semi-blind approach....... hiện toàn bộ
#Wireless communication #Intersymbol interference #Fading #Rayleigh channels #Matched filters #Detectors #Land mobile radio #Decision feedback equalizers #Resonance light scattering #Filtering
Memory synthesis for low power ASIC design
- Trang 335-342
In this paper we describe a multi-module, multiport memory design procedure that satisfies area and/or energy constraints. Our procedure consists of using ILP models and heuristic-based algorithms to determine (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy cons...... hiện toàn bộ
#Application specific integrated circuits #Energy consumption #Heuristic algorithms #Costs #Electrocardiography #Very large scale integration #Focusing #Multidimensional systems #Streaming media #Video sequences
A new low-voltage CMOS 1-bit full adder for high performance applications
- Trang 21-24
In this paper, a new low-voltage high-performance CMOS 1-bit full adder circuit is proposed. The new design is derived by combining XOR (XNOR) gates, used in the conventional full adder, and transmission gates. The proposed full adder can provide full voltage swing at a low supply voltage and offers superior performance in both power and speed than the conventional full adder, the transmission ful...... hiện toàn bộ
#Adders #Low voltage #Very large scale integration #Power supplies #Power dissipation #CMOS technology #Digital signal processing #Batteries #Circuit synthesis #Energy consumption