A novel systolic VLSI architecture for fast RSA modular multiplication
Proceedings. IEEE Asia-Pacific Conference on ASIC, - Trang 81-84
Tóm tắt
In this paper, we present a novel systolic VLSI architecture for performing fast modular multiplication in RSA cryptosystem. First, we propose a modified version of Montgomery's modular multiplication algorithm using a precomputed addition result, and then the proposed algorithm is mapped onto linear systolic arrays of processing elements for modular multiplication. Our implementation results have shown that the proposed systolic VLSI architecture is suitable for implementing high performance RSA cryptosystem, compared to conventional Montgomery's algorithm.
Từ khóa
#Very large scale integration #Public key cryptography #Computer architecture #Hardware #Systolic arrays #Computer science #Data communication #Business #Digital signatures #ArithmeticTài liệu tham khảo
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