A 33 mW 12-bit 100 MHz sample-and-hold amplifier
Proceedings. IEEE Asia-Pacific Conference on ASIC, - Trang 169-172
Tóm tắt
A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 /spl mu/m CMOS technology, the SHA achieves 73 dB SFDR for 2 Vpp input at 100 MHz sampling rate. The performance is not degraded for input frequency up to the Nyquist frequency. Power consumption is 33 mW from a single 2.5 V supply.
Từ khóa
#Sampling methods #Clocks #Capacitors #Switches #Analog-digital conversion #CMOS technology #Frequency #Signal resolution #Bandwidth #VoltageTài liệu tham khảo
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