IEEE Transactions on Electron Devices

Organic light-emitting diodes made of tris-8-(hydroxyquinoline) aluminum as the electron-transport layers, N, N'-diphenyl-N, N' bis (3-methylphenyl)-1, 1'-biphenyl-4,4'-diamine (TPD) as the hole-transport layers, and 2-1, 1-dimethylethyl-62-2, 3, 6, 7-tetrahydro-1, 1, 7, 7-tetramethyl-1H, 5H-benzo(ij) quinolizin-9-yl ethenyl-4H-pyran-4-ylidene propanedinitrile (DCJTB) as the guest dopant have been studied. It is determined that (a) emission from guest DCJTB in a host transport material results primarily from separate trapping of holes and electrons, rather than the more commonly proposed Forster transfer mechanism, (b) DCJTB is a more efficient hole than electron trap, and (c) the lifetime of a doped device is longer when TPD is used as the host material.

This paper proposes a novel structure of the conical Si field emitters monolithically incorporating a vertical-type junction field effect transistor (JFET) and demonstrates the emission control in field emission from the emitters. The proposal has many attractive advantages in the display application and reliable fabrication, because the structure needs neither additional area for the JFET nor additional process except ion implantation. The experimental results of the emitters show excellent controllability and stability in the emission current.

In order to select the optimal device for a particular application, designers must carefully analyze the tradeoffs between competing devices. Recent progress in SiC power rectifiers has resulted in the demonstration of high-voltage PiN and Schottky barrier diodes (SBDs). With both technologies maturing, power electronics engineers will soon face the task of selecting between these two devices. Until recently, the choice was simple, since silicon SBDs are only available for relatively low voltage applications. The choice is not as clear when considering SiC diodes, and guidelines for determining the proper application of each are needed. The purpose of this paper is to provide such guidelines, based on an analysis of the most significant tradeoffs involved.

We have proposed and fabricated a novel 50-nm nMOSFET with side-gates, which induce inversion layers for virtual source/drain extensions (SDE). The 50-nm nMOSFETs show excellent suppression of the short channel effect and reasonable current drivability [subthreshold swing of 86 mV/decade, drain-induced barrier lowering (DIBL) of 112 mV, and maximum transconductance (g/sub m/) of 470 /spl mu/S//spl mu/m at V/sub D/=1.5 V], resulting from the ultra-shallow virtual SDE junction. Since both the main gate and the side-gate give good cut-off characteristics, a possible advantage of this structure in an application to multi-input NAND gates was investigated.

In this paper, a new microthyristor structure suitable for microelectronics applications has been introduced. A suitable technology for its implementation has been chosen. The microthyristor has been designed and its performance has been simulated. The device showed superior performance concerning the switching times and the power dissipation in addition to controllability of its S-curve. During the development of this work, we introduced some new concepts such as doping-engineered devices, thyristor turn-off by shunting its cathode junction, and power consumption reduction by realizing high resistances. The basic requirements and some conditions are put together for successful launch of the microthyristor in microelectronics.

Two-step recess gate technology has been developed for sub-100-nm gate InP-based InAlAs/InGaAs high-electron mobility transistors (HEMTs). This gate structure is found to be advantageous for the preciseness of the metallurgical gate length as well as a comparable stability to the conventional gate structure with an InP etch stop layer. The two-step recess gate is optimized focusing on the lateral width of the gate recess. Due to the stability of the gate recess with an InP surface, a laterally wide gate recess gives the maximum cutoff frequency, lower gate leakage current, smaller output conductance and higher maximum frequency of oscillation. Finally, the uniformity of the device characteristics evaluated for sub-100-nm HEMTs with the optimized recess width. The result reveals the significant role of the short channel effects on the device uniformity.

Scaling of analog CMOS in the deep submicron regime is challenging, particularly for mixed mode system on chip applications due to the tradeoff in design requirements for analog and digital applications. The conventional approach employing aggressive gate oxide and S/D junction scaling to suppress the two-dimensional (2-D) electrostatic coupling and related short channel effects that degrade the device behavior in the deep submicron regime, though, improves the digital performance. However, this approach is not sufficient to obtain a reasonable analog performance. This paper presents a comprehensive study on the analog performance of scaled MOSFETs and explores alternative ways for improving the analog performance of these devices. It is shown that an easily integrable innovative channel engineering scheme in the form of single pocket structures can be used in the standard logic CMOS process to significantly improve the device analog performance of the deep submicron devices.

We report the importance of oxynitridation using radical-oxygen and -nitrogen to form a low-leakage and highly reliable 1.6-nm SiON gate-dielectric without performance degradation in n/pFETs. It was found that oxidation using radical-oxygen forms high-density 1.6-nm SiO/sub 2/, which is ten times more reliable than low-density SiO/sub 2/ formed by oxygen-ions in n/pFETs and is suitable for the base layer of nitridation. Nitrifying SiO/sub 2/ using radical-nitrogen facilitates surface nitridation of SiO/sub 2/, maintains an ideal SiON-Si substrate interface, and reduces the gate leakage current. The 1.6-nm SiON formed by radical-oxygen and -nitrogen produces comparable drivability in n/pFETs, has one and half orders of magnitude less gate leakage in nFETs, one order of magnitude less gate leakage in pFETs, and is ten times more reliable in n/pFETs than 1.6-nm SiO/sub 2/ formed by radical-oxygen.

A numerical analysis of the electrical characteristics for the ferroelectric memory field-effect transistors (FeMFETs) is presented. Two important structures such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMISFET) are considered. A new analytic expression for the relation of polarization versus electric field (P-E) is proposed to describe the nonsaturated hysteresis loop of the ferroelectric material. In order to provide a more accurate simulation, we incorporate the combined effects of the nonsaturated polarization of ferroelectric layers and the nonuniform distributions of electric field and charge along the channel. We also discuss the possible nonideal effects due to the fixed charges, charge injection, and short channel. The present theoretical work provides some new design rules for improving the performance of FeMFETs.