Symposium 1989 on VLSI Circuits
Cơ quản chủ quản: N/A
Lĩnh vực:
Các bài báo tiêu biểu
11.5ns 1M x 1/256K x 4TTL BiCMOS SRAM's with voltage- and temperature-compensated interfaces
- 1989
In high speed SRAM's a ground bounce noise caused by package lead inductance is serious limitation of access time.
#Random access memory #BiCMOS integrated circuits #Temperature dependence #Delays #Current mirrors #Thermal stability #Photomicrography
A circuit design for 2 Gbit/s Si brpolar crosspoint switch LSIs
- 1989
A SI bipolar circuits technology for Gblt/s crosspoint switch LSIs Is described. Adopting a new circuit design and a Super Self-aligned process Technology (SST-IA), an 8x8 and a 16x16(+16) crosspoint switch LSis are fabricated.
#Switches #Large scale integration #Switching circuits #Latches #Silicon #Circuit synthesis #Multiplexing
A versatile data-transfer control unit for a parallel processor system
- 1989
VLSI parallel processor system is one of promising candidates for the future machine to carry out hevy-duty numerical computation. For the parallel system, not only PE(processor element) operation speed but also inter-PE data transfer is very important to achieve high performance. Especially, in the parallel processor system with localized memories and a connection network, there are two major que......
#Layout #Generators #Data transfer #Adders #Registers #Transistors #Process control
A modularized speech recognition processor LSI with a highly parallel structure
- 1989
To actualize a continuous speech recognition System with a large vocabulary, we proposed ring-array-processor architecture [1-2], This architecture has the two features: highly parallel DTW(Dynamize Time Warping) processing [31 capability. which is the main algorithm used to realize speech recognition. and array size flexibility. which makes it possible to determine the number of PE(processing Ele......
#Parallel processing #Speech recognition #Layout #Vocabulary #Very large scale integration #Data transfer #Arrays
An 8 bit 100 MHz 3 channel CMOS DAC with analog switching current cells
- 1989
This paper describes an 8 bit 3 channel CMOS D/ A converter which bas a small cell area and has achieved a lOOMHz conversion rate, a low glitch energy of 6OpVs. and good linearity matching among 3 channels. The highest conversion rate of an 8 bit 3 channel CMOS DAC so far is 50nHz and glitch level is around 1OOpVs.
#Linearity #Switches #Transistors #Logic gates #Clocks #Matrix converters #Digital-analog conversion
Author index
- Trang 132-134 - 1989
The author index contains an entry for each author and coauthor included in the proceedings record.
#Indexes
Programmable vector-matrix multipliers for artificial neural networks
- 1989
A vector matrix multiply operation is a general function needed for the vast majority of neural network algorithms.
#Differential amplifiers #Logic gates #Linearity #Capacitors #Impedance #Very large scale integration #MOSFET
An eyperimental 1Mb cache DRAM with ECC
- 1989
In the recent progress of the micro processor unit (MPU), requirements for fast access aped memories have become strong. And a cost-effective cache subsystem is desired for the low-end work station and the personal computer. On the other hand, as for DRAMs, problems of the reliability such as α-particle induced soft errors will be more serious according to the increase of density.
#Random access memory #Error correction codes #Arrays #Cache memory #System-on-chip #Error correction #DRAM chips
A circuit design to suppress asymmetrical characteristics in 16-Mbit DRAM sense amplifier
- 1989
Recently, l6-Mbit DRAMS have been designed and fabricated using submicron CMOS technology. However, the submicron MOSFETs with LDD or Efficient Punch through Stop (EPS) structure 111 have serious problems-such as 1) the drain current asymmetry, 2) the threshold voltage difference , and 3) the gate/source capacitance imbalance.
#Logic gates #Transistors #Sensitivity #Random access memory #MOSFET #Threshold voltage #Circuit synthesis
An 8 bit, 200 MHz BiCMOS comparator
- 1989
A BiCMOS comparator intended for use in low-power, high-speed analog-t-digital conversion systems operating at video frequencies and above is described. An experimental version of the comparator integrated in a 1μm BiCMOS technology performs comparisons at mtes up to 200 MHE.
#Voltage measurement #BiCMOS integrated circuits #Capacitors #Clocks #Switches #Frequency measurement #Latches