Symposium 1989 on VLSI Circuits
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Các bài báo tiêu biểu
A circuit design for 2 Gbit/s Si brpolar crosspoint switch LSIs
- 1989
A SI bipolar circuits technology for Gblt/s crosspoint switch LSIs Is described. Adopting a new circuit design and a Super Self-aligned process Technology (SST-IA), an 8x8 and a 16x16(+16) crosspoint switch LSis are fabricated.
#Switches #Large scale integration #Switching circuits #Latches #Silicon #Circuit synthesis #Multiplexing
A 4ns 16k BiCMOS SRAM
- 1989
A 2K x 8bit ECL 100K compatible BiCMOS SRAM with 4 ns (60°, - 4.5V) address access time is reported.
#Random access memory #BiCMOS integrated circuits #Power dissipation #MOSFET #Transistors #Latches #Decoding
High performance BiCMOS circuit technology VLSI gate arrays
- 1989
This paper discusses the design and technology for a high density, full BiCMOS channelless gate array. A gate delay of 360ps lor a 0.4pf load has been achieved on a 106k gate (2- input NAND equivalent) test chip.
#Logic gates #BiCMOS integrated circuits #Transistors #Delays #Capacitance #Integrated circuit interconnections #Layout
Circuit design of a 9ns-HIT-delay 32K byte cache macro
- 1989
After a Reduced Instruction Set Computer (RISC) was shown to be effective in increasing CPU performance, several attempts have teen made to further improve the CPU performance by including cache memory an the same chipl21. However, the formerly reported cache size is limited up to 2K bytes. which is not sufficient to obtain more than 95% hit rate. This paper describes a 32K byte cache macro with a......
#Delays #Pipelines #Latches #Logic gates #Cache memory #System-on-chip #Reduced instruction set computing
A TV(UHF/VHF)/Fm/AM compatible Bi-CMOS 1GHz single chip PLL IC
- 1989
Wide band single chip PLL IC is required for receiving the broadcasting signal from long wave to TV UHF an a radio cassette tape recorder and a car radio. Input signal ranges from 0.5MHz to I GHz in frequency.
#Phase locked loops #MOS devices #Tuning #TV #Sensitivity #Voltage-controlled oscillators #Switches
11.5ns 1M x 1/256K x 4TTL BiCMOS SRAM's with voltage- and temperature-compensated interfaces
- 1989
In high speed SRAM's a ground bounce noise caused by package lead inductance is serious limitation of access time.
#Random access memory #BiCMOS integrated circuits #Temperature dependence #Delays #Current mirrors #Thermal stability #Photomicrography
An 8-bit 20 MS/s CMOS A/D converter with 59 mW power consumption
- 1989
Digital signal processing has been widely introduced in video systems. In these systems, CMOS A/D converters (ADCs) with low power consumption and small chip area are especially desirable as on-chip area are especially desirable as on-chip area are especially desirable as on-chip devices.
#Power demand #Analog-digital conversion #Timing #Generators #Capacitors #CMOS technology #TV
Design of a CMOS token ring LAN controller, TRC, compatible with IEEE802.5 MAC protocol
- 1989
Token ring has been increasing its importance among LAN (local area network) protocol as the need for deterministic response and low cost wirings continues to grow[1][2][3]. However, its complexity has caused multiple chip solutions for controllers, which are power and space consuming. Taking advantage of advanced CMOS circuits, we have newly developed a single chip high performance token ring con......
#Clocks #Random access memory #Read only memory #Registers #Hardware #Standards #Protocols
A new staggered virtual ground array architecture implemented in a 4Mb CMOS EPROM
- 1989
A new array architecture Is Introduced which Is suitable for very high density €PROMS. For a given set of design rules, this approach yields 40% Smaller array size compared to previous array architectures. The Staggered Virtual Ground (SVG) array has been Implemented based on the split gate EPROM technology. A dual function column muxing scheme and Address Transition Detection design techniques ha......
#EPROM #Logic gates #III-V semiconductor materials #Aluminum nitride #Tungsten #CMOS technology #Throughput
A self-timed dynamic sensing scheme for 5V only multi-Mb flash E/sup 2/PROMs
- 1989
In recent years, several types of flash E'PROM have been proposed to enhance the density of electrically alterable non-volatile memories. However, shrinking the memory cell causes the reduction of the cell current, 80 that a sensitive sensing scheme has been required, which replaces the conventional current sensing. A simultaneous multi-bit reading is also necessary for L high speed serial and pag......
#Sensors #Flip-flops #Timing #Electric potential #Current measurement #Size measurement #Semiconductor device measurement