Symposium 1989 on VLSI Circuits
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A latch-up like new failure mechanism for high density cmos dynamic RAM's - hysteresis in operating Vcc range
- 1989
AS the RAM has reached higher Integration, transistors have been miniaturized as
well as the number of transistors on a chip has increased. Therefore, the
substrate current generated by the RAM circuit due to impact ionization has
increased drastically. In addition, since substrate impurity concentration has
increased with the device scaling, the back-gate bias effect of a transistor has
become st...
#Random access memory #Substrates #Amplitude modulation #Transistors #Hysteresis #Threshold voltage #Couplings
A monolithically integrated fiber-optic front-end receiver in GaAs Si technology
- 1989
A fiber-optic receiver front-end integrated in B monolithic GaAr on silicon
technology is described. In this circuit an interdigitated GaAs
metal-semiconductor-metal photodetector is combined with a transimpedance
preamplifier fabricated in silicon bipolar technology. The integrated receiver
is designed to operate with il bandwidth of 1GRz and a preamplifier
transimpedance of 5kΩ.
#Silicon #Preamplifiers #Gallium arsenide #Capacitance #Optical fibers #Photodiodes #Integrated circuit interconnections
Author index
- Trang 132-134 - 1989
The author index contains an entry for each author and coauthor included in the
proceedings record.
#Indexes
A review of superconducting three-terminal devices
- 1989
Superconducting three-terminal devices have been extensively given attention as
one of future digital devices since Bcdnorz and Mueller discovered
high-critical-temperature superconductivity in the La-Ba-Cu-0 system. The use of
zero-resistance superconductivity and low noise cryogenics is expectcd for a
limiting field of silicone semiconductor devices. In this paper, it is
worthwhile to review som...
#Superconductor devices #Digital systems #Temperature measurement
Programmable vector-matrix multipliers for artificial neural networks
- 1989
A vector matrix multiply operation is a general function needed for the vast
majority of neural network algorithms.
#Differential amplifiers #Logic gates #Linearity #Capacitors #Impedance #Very large scale integration #MOSFET
A data flow image compression processor
- Trang 119-120 - 1989
This paper presents a binary image data compression and expansion processor that
can compress 500 kbytes of image data into 35 kbyles of code data in 0.41
seconds. The processor equips with data flow hardware and CPU on the one chip.
Topics described include the algorithms, architecture, and performance.
#Image coding #Image color analysis #Central Processing Unit #Pipeline processing #Facsimile #Decoding #Dams
Circuit design of a 9ns-HIT-delay 32K byte cache macro
- 1989
After a Reduced Instruction Set Computer (RISC) was shown to be effective in
increasing CPU performance, several attempts have teen made to further improve
the CPU performance by including cache memory an the same chipl21. However, the
formerly reported cache size is limited up to 2K bytes. which is not sufficient
to obtain more than 95% hit rate. This paper describes a 32K byte cache macro
with a...
#Delays #Pipelines #Latches #Logic gates #Cache memory #System-on-chip #Reduced instruction set computing
A TV(UHF/VHF)/Fm/AM compatible Bi-CMOS 1GHz single chip PLL IC
- 1989
Wide band single chip PLL IC is required for receiving the broadcasting signal
from long wave to TV UHF an a radio cassette tape recorder and a car radio.
Input signal ranges from 0.5MHz to I GHz in frequency.
#Phase locked loops #MOS devices #Tuning #TV #Sensitivity #Voltage-controlled oscillators #Switches
High-reliability and high-speed design of 1Mb CMOS SRAM with 0.5/spl mu/m devices
- 1989
A 13- 1Mb CMOS SRAM fabricated with triple polysilicon, double metal layers and
0.5~ gate MOS FET's will be described. The RAM utilizes the divided
double-word-line scheme and three stage sense ampli6ers for high-speed
operation. MMWV~L performance of the RAM is enhanced by 0.5μm MOS devices fully
used in the internal circuits. An on-chip voltage down converter ( VDC ) is well
designed to supply t...
#Random access memory #Logic gates #Computer architecture #Microprocessors #Delays #Organizations #Decoding
A 68ns 4Mbit CMOS EPROM with high noise immunity design
- 1989
High speed non-volatile memories with large bit density have been required for
high performance micro-processor systems. Sub 100ns-access time 4Mbit EPROMs[1],
[2] have been, developed to meet the marlre1 needs.
#EPROM #Capacitance #Dams #Logic gates #Threshold voltage #Sensors #Delays