Symposium 1989 on VLSI Circuits
Cơ quản chủ quản: N/A
Các bài báo tiêu biểu
An 8 bit, 200 MHz BiCMOS comparator
- 1989
A BiCMOS comparator intended for use in low-power, high-speed analog-t-digital
conversion systems operating at video frequencies and above is described. An
experimental version of the comparator integrated in a 1μm BiCMOS technology
performs comparisons at mtes up to 200 MHE.
#Voltage measurement #BiCMOS integrated circuits #Capacitors #Clocks #Switches #Frequency measurement #Latches
A speed enhancement DRAM array architecture with embedded ECC
- 1989
A scaling down principle brings a high speed switching and a low power
dissipation with the reliability maintained [I-21. In addition to the dimension
scaling down. an epoch-making array architecture with the countermeasure of
smaller signal charge is required in a high speed 16MbDRAH.
#Computer architecture #Arrays #Microprocessors #Error correction codes #Random access memory #Logic gates #Distributed databases
A review of superconducting three-terminal devices
- 1989
Superconducting three-terminal devices have been extensively given attention as
one of future digital devices since Bcdnorz and Mueller discovered
high-critical-temperature superconductivity in the La-Ba-Cu-0 system. The use of
zero-resistance superconductivity and low noise cryogenics is expectcd for a
limiting field of silicone semiconductor devices. In this paper, it is
worthwhile to review som...
#Superconductor devices #Digital systems #Temperature measurement
An on-chip smart memory for a data flow CPU
- 1989
Register Alias Table (RAT) is an on-chip Smart memory for HPSm . a Berkeley data
Row CPU. It is a multiport memory that has content addressability, support for
branch prediction and exception handling in addition to conventional read and
write operations. It is implemented in a 1.6μ double metal CMOS process. This
memory performs 15 operations within a cycle time of 1031s. has 34,658
transistors, ...
#Radio access technologies #Central Processing Unit #Decoding #System-on-chip #Random access memory #Out of order #Writing
CMOS subnanosecond true-ECL output buffer
- 1989
This paper presents, for the first time, a CMOS output buffer circuit compatible
with standard ECL lOOk systems and not needing external components or additional
supply voltages. High speed (0.9 ns delay), sufficient precision and good
pulse-response are achieved through use of a new circuit principle. The circuit
has been fabricated in an 0.7 μm memory process.
#Transistors #Delays #Capacitance #Logic gates #Circuit stability #Voltage measurement #Transmission line measurements
SPL (super push-pull logic) a bipolar novel low-power high-speed logic circuit
- 1989
In this contribution we would like to present a new bipolar low -power high
-speed logic circuit named SPL (Super Push-pull Logic). At a low POY~~ per gate
range of lmw/gate, the calculated path propagation delay time of SPL gates
loading wire capacitances of 0.57pF/gate is 2.75 times faster than the one of
conventional ECL(Emitter Coupled Logic) gates.
#Logic gates #Capacitance #Delays #Transistors #Loading #Wires #Large scale integration
A 2 GHz clock direct frequency synthesiser
- 1989
First results are now available on a U.H.F. capable Direct Frequency
Synthesiser, (DFS) which is primarily intended for radar and E.W. applications.
The device generates square, mangle and sine wave outputs, me and complement,
phase and quadrature, over the range 1Hz to 500MHz.
#Clocks #Synthesizers #Read only memory #Frequency synthesizers #Transistors #Phase locked loops #Performance evaluation
Circuit design of a 9ns-HIT-delay 32K byte cache macro
- 1989
After a Reduced Instruction Set Computer (RISC) was shown to be effective in
increasing CPU performance, several attempts have teen made to further improve
the CPU performance by including cache memory an the same chipl21. However, the
formerly reported cache size is limited up to 2K bytes. which is not sufficient
to obtain more than 95% hit rate. This paper describes a 32K byte cache macro
with a...
#Delays #Pipelines #Latches #Logic gates #Cache memory #System-on-chip #Reduced instruction set computing
A 68ns 4Mbit CMOS EPROM with high noise immunity design
- 1989
High speed non-volatile memories with large bit density have been required for
high performance micro-processor systems. Sub 100ns-access time 4Mbit EPROMs[1],
[2] have been, developed to meet the marlre1 needs.
#EPROM #Capacitance #Dams #Logic gates #Threshold voltage #Sensors #Delays
Analog-to-digital converter with non-linear capacitor compensation
- 1989
One of the sources of non-linearity in charge-redistribution analog-to-digital
converters (ADCs) is capacitor voltage dependence. This paper will discuss
Circuit techniques lo eliminate conversion errors caused by the capacitor
voltage dependence, and performance data from circuits realized in a linear CMOS
process will be presented.
#Capacitors #Signal generators #Registers #Linearity #Topology #MOS capacitors #Integrated circuit modeling