Symposium 1989 on VLSI Circuits
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An 8 bit, 200 MHz BiCMOS comparator
- 1989
A BiCMOS comparator intended for use in low-power, high-speed analog-t-digital conversion systems operating at video frequencies and above is described. An experimental version of the comparator integrated in a 1μm BiCMOS technology performs comparisons at mtes up to 200 MHE.
#Voltage measurement #BiCMOS integrated circuits #Capacitors #Clocks #Switches #Frequency measurement #Latches
Soft-error characteristics in bipolar memory cells with small critical charge
- 1989
In this paper, first, the contribution of charge collected at the base and the collector to soft-error is investigated using computer simulation. Next, an effective charge model incorporating weight coefficients is proposed.
#Sensitivity #Random access memory #Integrated circuit modeling #Life estimation #Discharges (electric) #Computational modeling #Alpha particles
Automatic gain control (AGC) circuit for high density BiCMOS SRAM
- 1989
In this paper an Automatic Gain Control (AGC) circuit is discussed. This AGC circuit is applied to a high speed BiCMOS SRAM bitline scheme to control the bitline voltage swings so that they are independent of temperature, operation and process variations.
#BiCMOS integrated circuits #Random access memory #Gain control #Voltage control #Transistors #Operational amplifiers #Resistors
A low power time-multiplexed SC speech spectrum analyzer
- 1989
A Low Power Time-Multiplexed Switched Capacitor Speech Spectrum Analyzer embodying several novel circuit designs is described. Expressions for errors that limit the accuracy of the running spectrum an derived. A four channel speech spectrum analyzer has been fabricated
#Filter banks #Operational amplifiers #Semiconductor device measurement #Hardware #Speech recognition #Frequency measurement #Clocks
A speed enhancement DRAM array architecture with embedded ECC
- 1989
A scaling down principle brings a high speed switching and a low power dissipation with the reliability maintained [I-21. In addition to the dimension scaling down. an epoch-making array architecture with the countermeasure of smaller signal charge is required in a high speed 16MbDRAH.
#Computer architecture #Arrays #Microprocessors #Error correction codes #Random access memory #Logic gates #Distributed databases
The stabilized reference-line (SRL) technique for scaled DRAMs
- 1989
Recently it has been reported that bitline interference noise increases with DRAM integration and that reduction of this noise is the key issue to realizing 16Mb DRAMs and beyond.(l) In order to reduce this interference noise.
#Interference #Random access memory #Generators #Noise measurement #Couplings #Clocks #Capacitance
A latch-up like new failure mechanism for high density cmos dynamic RAM's - hysteresis in operating Vcc range
- 1989
AS the RAM has reached higher Integration, transistors have been miniaturized as well as the number of transistors on a chip has increased. Therefore, the substrate current generated by the RAM circuit due to impact ionization has increased drastically. In addition, since substrate impurity concentration has increased with the device scaling, the back-gate bias effect of a transistor has become st......
#Random access memory #Substrates #Amplitude modulation #Transistors #Hysteresis #Threshold voltage #Couplings
A 68ns 4Mbit CMOS EPROM with high noise immunity design
- 1989
High speed non-volatile memories with large bit density have been required for high performance micro-processor systems. Sub 100ns-access time 4Mbit EPROMs[1], [2] have been, developed to meet the marlre1 needs.
#EPROM #Capacitance #Dams #Logic gates #Threshold voltage #Sensors #Delays
High performance VLSI processor architectures
- 1989
Single-chip processor performance has improved dramatically since the inception of the four-bit microprocessor in 1971. This is due in part to technological advances (i.e., faster devices and greater device density), but also because of the adoption of architectural approaches well suited to the opportunities and limitations of VLSI. These approaches reduce off-chip memory accesses and admit of a ......
#Instruction sets #Pipeline processing #Clocks #Transistors #Complexity theory #Registers #Computer architecture
SPL (super push-pull logic) a bipolar novel low-power high-speed logic circuit
- 1989
In this contribution we would like to present a new bipolar low -power high -speed logic circuit named SPL (Super Push-pull Logic). At a low POY~~ per gate range of lmw/gate, the calculated path propagation delay time of SPL gates loading wire capacitances of 0.57pF/gate is 2.75 times faster than the one of conventional ECL(Emitter Coupled Logic) gates.
#Logic gates #Capacitance #Delays #Transistors #Loading #Wires #Large scale integration