Symposium 1989 on VLSI Circuits
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A latch-up like new failure mechanism for high density cmos dynamic RAM's - hysteresis in operating Vcc range
- 1989
AS the RAM has reached higher Integration, transistors have been miniaturized as
well as the number of transistors on a chip has increased. Therefore, the
substrate current generated by the RAM circuit due to impact ionization has
increased drastically. In addition, since substrate impurity concentration has
increased with the device scaling, the back-gate bias effect of a transistor has
become st...
#Random access memory #Substrates #Amplitude modulation #Transistors #Hysteresis #Threshold voltage #Couplings
A sub-ns clock josephson 4b processor
- 1989
We constructed a 4h processor with a Lh slice microprocessor, 4b multiplier, 12b
accumulator, 8Kb ROM and sequencer. The chip was fabricated with 1.5-um
all-niobium technology, and contains 24,000 Nb/AlO,/Nb Josephson junctions. The
processor vas operated up to 1.1 GRz under worst-case conditions, dissipating
6.1 mW.
#Logic gates #Microprocessors #Clocks #Read only memory #Pipelines #Junctions #Delays
An expermental 16Mb DRAM with reduced peak-current noise
- 1989
In high-density DRAM'S, a large peak current of typically 200-300mA occurs when
sense amplifiers start latching in a conventional scheme (Figure la), resulting
in intolerable power bus noise. Four-phase drive for PMOS restoring was reported
to reduce the peak current by triggering four pull-up transistors
successively.[l] The initial sensing operation by NMOS latches, however, is more
critical to ...
#Random access memory #Sensors #Transistors #Latches #Process control #Photomicrography #Metals
An experimental 27w 1Mb CMOS high-speed DRAM
- 1989
In recent years, high-speed DRAMs[ll are in greater demand as microprocessors
become faster. In a small microprocessor-based computer system. high-speed DRAMS
can keep up with the CPU and avoid wait states during memory accesses. This
paper describes an experimental 256 K word X 4 bit CMOS DRAM with a typical RAS
access time of 27 ns. In page mode operation, a typical CAS access time of 12 ns
with...
#Random access memory #Delays #Generators #Temperature measurement #MOS devices #Substrates #Semiconductor device measurement
Soft-error characteristics in bipolar memory cells with small critical charge
- 1989
In this paper, first, the contribution of charge collected at the base and the
collector to soft-error is investigated using computer simulation. Next, an
effective charge model incorporating weight coefficients is proposed.
#Sensitivity #Random access memory #Integrated circuit modeling #Life estimation #Discharges (electric) #Computational modeling #Alpha particles
Automatic gain control (AGC) circuit for high density BiCMOS SRAM
- 1989
In this paper an Automatic Gain Control (AGC) circuit is discussed. This AGC
circuit is applied to a high speed BiCMOS SRAM bitline scheme to control the
bitline voltage swings so that they are independent of temperature, operation
and process variations.
#BiCMOS integrated circuits #Random access memory #Gain control #Voltage control #Transistors #Operational amplifiers #Resistors
Improving bandwidth and error rate in flash converters
- 1989
An B bit flash converter with 400 MEz analog bandwidth and new error correction
circuitry is described. A unique cascoded input stage and a dense 1.0 x 1.4 um
emitter, triple diffused bipolar process make the wide bandwidth possible. Three
different strategies are employed to keep errors low, even at the full 200 Msps
clock rate. An efficient error rate test system is also described.
#Error analysis #Latches #Error correction #Clocks #Capacitance #Read only memory #Measurement uncertainty
The stabilized reference-line (SRL) technique for scaled DRAMs
- 1989
Recently it has been reported that bitline interference noise increases with
DRAM integration and that reduction of this noise is the key issue to realizing
16Mb DRAMs and beyond.(l) In order to reduce this interference noise.
#Interference #Random access memory #Generators #Noise measurement #Couplings #Clocks #Capacitance
A low power time-multiplexed SC speech spectrum analyzer
- 1989
A Low Power Time-Multiplexed Switched Capacitor Speech Spectrum Analyzer
embodying several novel circuit designs is described. Expressions for errors
that limit the accuracy of the running spectrum an derived. A four channel
speech spectrum analyzer has been fabricated
#Filter banks #Operational amplifiers #Semiconductor device measurement #Hardware #Speech recognition #Frequency measurement #Clocks
"A 1.6ns 64kb ECL RAM with 1K gate logic"
- 1989
A 64K-bit density ECL RAM with 1K gate logic LSI, operating at a 1.6ns on-chip
access time, has been developed. The RAM has 1K-word x -bit x 16 block
organization and reconfigured as 2K-word x 8-bit x 4 block. The LSI has
feasibility of future advanced RAM with gate array application.
#Random access memory #Logic gates #Clocks #Organizations #Large scale integration #System-on-chip #Transistors