An eyperimental 1Mb cache DRAM with ECC

Symposium 1989 on VLSI Circuits - 1989
Asakura1, Matsuda1, Hidaka1, Tanaka1, Fujishima1, Yoshihara1
1LSI R & D Laboratory, Mitsubishi Electric Corporation Limited, Itami, Japan

Tóm tắt

In the recent progress of the micro processor unit (MPU), requirements for fast access aped memories have become strong. And a cost-effective cache subsystem is desired for the low-end work station and the personal computer. On the other hand, as for DRAMs, problems of the reliability such as α-particle induced soft errors will be more serious according to the increase of density.

Từ khóa

#Random access memory #Error correction codes #Arrays #Cache memory #System-on-chip #Error correction #DRAM chips

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Symposium 1989 on VLSI Circuits

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