International Conference on Simulation of Semiconductor Processes and Devices
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"What can computer aided engineering do for the SoC era ?"
- Trang 211-211 - 2002
TCAD has contributed to processldevice design and prediction of the device performances for decades. This role is still very important in very deep submicron process; however, new aspect in the semiconductor industry has arisen. Interconnect issue becomes more critical in SoC timing closure. ITRS roadmap predicts future of processldevices and interconnects, which lead to a standardized process and......
#Computer aided engineering #Timing #National electric code #Process design #Electronics industry #Technological innovation
Simulation and inverse modeling of TEOS deposition processes using a fast level set method
- Trang 191-194
Deposition and etching of silicon trenches is an important manufacturing step for state of the art memory cells. Understanding and simulating the transport of gas species and surface evolution enables to achieve void-less filling of deep trenches, to predict the resulting profiles, and thus to optimize process parameters with respect to manufacturing throughput and the quality of the resulting mem......
#Inverse problems #Level set #Predictive models #Computational modeling #Scanning electron microscopy #Etching #Silicon #Filling #Manufacturing processes #Virtual manufacturing
2D simulation of a buried-heterostructure tunable twin-guide DFB laser diode
- Trang 55-58
A 2D simulation of an InGaAsP-InP buried-heterostructure tunable twin-guide (TTG) DFB laser diode is performed. The device structure is optimized with respect to maximal tuning range and output power. To minimize the current leakage around the active region, a p-n-p-n current blocking region is also modeled and its effect on the laser characteristics is discussed. Good agreement between simulation......
#Tunable circuits and devices #Diode lasers #Laser tuning #Optical tuning #Laser modes #Distributed feedback devices #Optical refraction #Optical scattering #Equations #Quantum well lasers
Analysis of injection current with electron temperature for high-K gate stacks
- Trang 239-242
Though, high dielectric constant material is a possible near future candidate to suppress gate current densities of MOSFETs, the barrier height generally decreases with increasing dielectric constant. In this paper, the injection current through gate stacks has been calculated while taking into account the electron temperature using the W.K.B. method to understand the impact of the injection curre......
#Electrons #Temperature #High K dielectric materials #High-K gate dielectrics #Current density #Silicon #MOSFETs #Probability #Dielectric constant #Tunneling
Surface mobility in silicon at large operating temperature
- Trang 15-20
An experimental investigation on high-temperature carrier mobility in silicon inversion layers is carried out with the aim of improving our understanding of carrier transport at the onset of second breakdown. Special MOSFET structures suitable for Hall measurements were designed and manufactured using the BCD-3 technology available at ST-Microelectronics. Hall measurements were carried out using a......
#Silicon #Testing #Temperature distribution #Electric breakdown #MOSFET circuits #Temperature control #Manufacturing #Microelectronics #Impurities #Lattices
Transistor width dependence of LER degradation to CMOS device characteristics
- Trang 95-98
When transistor gate length is scaled down, the impact of transistor poly gate line edge roughness (LER) on device characteristics becomes significant. In this work, we study the dependence on transistor width of the low spatial frequency LER induced CMOS device Ion/Ioff degradations, based on TCAD simulation results and silicon data. Methodology to account for LER effects in device optimization i......
#Degradation #Scattering #Clouds #Intrusion detection #Silicon #Frequency #Optimization methods #Shape #CMOS technology #Instruments
A strategy for enabling predictive TCAD in development of sub-100nm CMOS technologies
- Trang 33-38
CMOS technology development is an expensive undertaking. Predictive TCAD can be a key tool in reducing the time and cost of CMOS development by acting as a virtual wafer fah where experimental lots are first simulated and the results analyzed before the first process step is ever run. In this way errors may be uncovered, poor splits eliminated and inadequate experimental designs improved. Each lot......
#CMOS technology #Implants #Semiconductor device modeling #Computational modeling #Semiconductor process modeling #Predictive models #Silicon #Space technology #Costs #Space exploration
Integrated atomistic process and device simulation of decananometre MOSFETs
- Trang 87-90
In this paper we present a methodology for the integrated atomistic process and device simulation of decananometre MOSFETs. The atomistic process simulations were carried out using the kinetic Monte Carlo process simulator DADOS, which is now integrated into the Synopsys 3D process and device simulation suite Taurus. The device simulations were performed using the Glasgow 3D statistical atomistic ......
#MOSFETs #Silicon #Fluctuations #Atomic measurements #Stochastic processes #Analytical models #Atomic layer deposition #Semiconductor process modeling #Kinetic theory #Monte Carlo methods
Realistic scaling scenario for sub-100nm embedded SRAM based on 3-dimensional interconnect simulation
- Trang 63-66
It is still an open problem to elucidate the scaling merit of the embedded SRAM with the Low Operating Power (LOP) MOSFET's fabrication in 50, 70 and 100nm CMOS technology node. Taking into account the realistic SRAM cell layout, we evaluate the parasitic capacitance of Bit Line (BL) as well as Word Line (WL) in each generation. By means of 3-Dimensional (3D) interconnect simulator (Raphael), we f......
#Random access memory #CMOS technology #Integrated circuit interconnections #Delay #Parasitic capacitance #Plugs #Circuit simulation #Large scale integration #Ultra large scale integration #Fabrication
Simulation of DGSOI MOSFETs with a Schrodinger-Poisson based mobility model
- Trang 21-24
Ultra-thin DGSOI transistors are considered as one of the most promising devices for future VLSI. Besides expected improvements in the sub-threshold behavior, a theoretical enhancement of the channel mobility was found by some authors. Here, we apply a quantum-mechanical mobility model, based on an integrated Schrodinger/Poisson solver, to double-gate SOI MOSFETs with a range of silicon slab thick......
#MOSFETs #Acoustic scattering #Particle scattering #Slabs #Semiconductor device modeling #Electrons #Electrostatics #Laboratories #Systems engineering and theory #Very large scale integration