International Conference on Simulation of Semiconductor Processes and Devices
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Các bài báo tiêu biểu
"What can computer aided engineering do for the SoC era ?"
- Trang 211-211 - 2002
TCAD has contributed to processldevice design and prediction of the device performances for decades. This role is still very important in very deep submicron process; however, new aspect in the semiconductor industry has arisen. Interconnect issue becomes more critical in SoC timing closure. ITRS roadmap predicts future of processldevices and interconnects, which lead to a standardized process and......
#Computer aided engineering #Timing #National electric code #Process design #Electronics industry #Technological innovation
Mô phỏng số hàm sóng hai hạt trong các dây lượng tử Dịch bởi AI
- Trang 175-178
Vì yêu cầu chính của máy tính lượng tử là việc tạo ra và khai thác sự ràng buộc, một nghiên cứu chi tiết về các trạng thái liên kết đã được thực hiện dựa trên một hệ thống rắn dựa trên các dây lượng tử liên kết. Đầu tiên, một tổng quan ngắn gọn về các cổng cơ bản được cung cấp, dựa trên các nghiên cứu sơ bộ, tiếp theo là phân tích các electron di chuyển dọc theo các dây lượng tử liên kết. Động lực......
#Numerical simulation #Wave functions #Wires #Electrons #Quantum computing #Quantum entanglement #Schrodinger equation #Coupling circuits #Circuit simulation #Analytical models
GIDL simulation and optimization for 0.13 /spl mu/m/1.5 V low power CMOS transistor design
- Trang 43-46
In this work, we calibrate a BTBT model based on measured GIDL data, and incorporate the model into our process/device simulations to directly correlate process with device performance and leakage. For the first time, we quantitatively explore an overall picture of tradeoffs between device leakage and performance as functions of process conditions. The explored design space has been used in proces......
#Design optimization #Tunneling #Space exploration #CMOS process #Medical simulation #MOS devices #Power measurement #Predictive models #Cost function #Current measurement
Analysis of injection current with electron temperature for high-K gate stacks
- Trang 239-242
Though, high dielectric constant material is a possible near future candidate to suppress gate current densities of MOSFETs, the barrier height generally decreases with increasing dielectric constant. In this paper, the injection current through gate stacks has been calculated while taking into account the electron temperature using the W.K.B. method to understand the impact of the injection curre......
#Electrons #Temperature #High K dielectric materials #High-K gate dielectrics #Current density #Silicon #MOSFETs #Probability #Dielectric constant #Tunneling
Integrated atomistic process and device simulation of decananometre MOSFETs
- Trang 87-90
In this paper we present a methodology for the integrated atomistic process and device simulation of decananometre MOSFETs. The atomistic process simulations were carried out using the kinetic Monte Carlo process simulator DADOS, which is now integrated into the Synopsys 3D process and device simulation suite Taurus. The device simulations were performed using the Glasgow 3D statistical atomistic ......
#MOSFETs #Silicon #Fluctuations #Atomic measurements #Stochastic processes #Analytical models #Atomic layer deposition #Semiconductor process modeling #Kinetic theory #Monte Carlo methods
A novel CDM-like discharge effect during human body model (HBM) ESD stress
- Trang 115-118
Interactions between ESD protection devices and other components of a chip can lead to complex and not easily anticipated discharge behaviour. Triggering of a protection MOSFET is equivalent to the closing of a fast switch and can cause substantial transient discharge currents. The peak value of this current depends on the chip capacitance, resistance, properties of the protection clamp, etc. Care......
#Humans #Biological system modeling #Electrostatic discharge #Stress #Protection #Switches #MOSFET circuits #Capacitance #Immune system #Clamps
2D simulation of a buried-heterostructure tunable twin-guide DFB laser diode
- Trang 55-58
A 2D simulation of an InGaAsP-InP buried-heterostructure tunable twin-guide (TTG) DFB laser diode is performed. The device structure is optimized with respect to maximal tuning range and output power. To minimize the current leakage around the active region, a p-n-p-n current blocking region is also modeled and its effect on the laser characteristics is discussed. Good agreement between simulation......
#Tunable circuits and devices #Diode lasers #Laser tuning #Optical tuning #Laser modes #Distributed feedback devices #Optical refraction #Optical scattering #Equations #Quantum well lasers
MOSFET hot-carrier induced gate current simulation by self-consistent silicon/oxide Monte Carlo device simulation
- Trang 231-234
Hot electron transport in MOS transistors is investigated by means of a coupled silicon/oxide Monte Carlo (MC) simulation. First, a new MC simulator able to handle selfconsistently different materials is developed. Then, the impact of oxide transport on the gate current (I/sub G/) is analyzed comparing different injection models with experiments. It is shown that oxide transport plays an important......
#MOSFET circuits #Hot carriers #Silicon #Monte Carlo methods #Integrated circuit modeling #Scattering #Potential well #Voltage #Electron emission #Computational modeling
An efficient algorithm for 3D interconnect capacitance extraction considering floating conductors
- Trang 107-110
With the inclusion of floating conductors in integrated circuits, conventional simulation tools exhibit prohibitive calculation times. A new simulation tool, called ICARE, was developed to extract efficiently the 3D capacitance matrix of interconnect structures embedded in a multi-layered dielectric environment. Using the so-called fictitious domain method, it leads to a coupled linear system, wit......
#Conductors #Dielectrics #Integrated circuit interconnections #Boundary conditions #Parasitic capacitance #Lagrangian functions #Integrated circuit modeling #Circuit simulation #Linear systems #Electric variables
Gate tunnelling and impact ionisation in sub 100 nm PHEMTs
- Trang 139-142
Impact ionization and thermionic tunnelling as two possible breakdown mechanisms in scaled pseudomorphic high electron mobility transistors (PHEMTs) are investigated by Monte Carlo (MC) device simulations. Impact ionization is included in MC simulation as an additional scattering mechanism whereas thermionic tunnelling is treated in the WKB approximation during each time step in selfconsistent MC ......
#Tunneling #Impact ionization #PHEMTs #Threshold voltage #Electric breakdown #Electron mobility #HEMTs #MODFETs #Monte Carlo methods #Scattering