Danh mục bài báo

International Conference on Simulation of Semiconductor Processes and Devices

Công bố khoa học tiêu biểu của tạp chí. * Dữ liệu chỉ mang tính chất tham khảo

Sắp xếp

On the large-signal CMOS modeling and parameter extraction for RF applications

International Conference on Simulation of Semiconductor Processes and Devices· ·Trang 67-70

Minkyu Je, Ickjin Kwon, Jeonghu Han, Hyungcheol Shin, Kwyro Lee

#Semiconductor device modeling #Parameter extraction #Radio frequency #Equivalent circuits #MOSFET circuits #Scattering parameters #Capacitance #Integrated circuit modeling #Circuit simulation #Data mining

Realistic scaling scenario for sub-100nm embedded SRAM based on 3-dimensional interconnect simulation

International Conference on Simulation of Semiconductor Processes and Devices· ·Trang 63-66

Y. Tsukamoto, T. Kunikiyo, K. Nii, H. Makino, S. Iwade, K. Ishikawa, Y. Inoue

#Random access memory #CMOS technology #Integrated circuit interconnections #Delay #Parasitic capacitance #Plugs #Circuit simulation #Large scale integration #Ultra large scale integration #Fabrication

Analysis of injection current with electron temperature for high-K gate stacks

International Conference on Simulation of Semiconductor Processes and Devices· ·Trang 239-242

Y. Ohkura, H. Takashino, S. Wakahara, K. Nishi

#Electrons #Temperature #High K dielectric materials #High-K gate dielectrics #Current density #Silicon #MOSFETs #Probability #Dielectric constant #Tunneling

Ensemble Monte Carlo/molecular dynamics simulation of inversion layer mobility in Si MOSFETs - effects of substrate impurity

International Conference on Simulation of Semiconductor Processes and Devices· ·Trang 25-28

Y. Kamakura, H. Ryouke, K. Taniguchi

#Monte Carlo methods #MOSFETs #Electromagnetic compatibility #Electron mobility #Substrates #Impurities #Particle scattering #Information systems #FETs #Threshold voltage

Finite element analysis of stress evolution in Si based front and back ends micro structures

International Conference on Simulation of Semiconductor Processes and Devices· ·Trang 247-252

V. Senez, A. Armigliato, G. Carlotti, G. Carnevale, H. Jaouen, I. de Wolff

#Finite element methods #Stress #Silicon #Manufacturing #Microelectronics #Numerical simulation #Geometry #Numerical models #Electron beams #Predictive models

A new gate current model accounting for a non-Maxwellian electron energy distribution function

International Conference on Simulation of Semiconductor Processes and Devices· ·Trang 235-238

A. Gehring, T. Grasser, H. Kosina, S. Selberherr

#Distribution functions #Shape #Tunneling #Monte Carlo methods #MOSFET circuits #Secondary generated hot electron injection #Tail #Lattices #Temperature distribution #Microelectronics

An efficient algorithm for 3D interconnect capacitance extraction considering floating conductors

International Conference on Simulation of Semiconductor Processes and Devices· ·Trang 107-110

O. Cueto, F. Charlet, A. Farcy

#Conductors #Dielectrics #Integrated circuit interconnections #Boundary conditions #Parasitic capacitance #Lagrangian functions #Integrated circuit modeling #Circuit simulation #Linear systems #Electric variables

Hot-carrier energy distribution model and its application to the MOSFET substrate current

International Conference on Simulation of Semiconductor Processes and Devices· ·Trang 171-173

Chang-sub Lee, Gyoyoung Jin, Keun-ho Lee, Jeong-taek Kong, Won-seong Lee, Yong-han Rho, E.C. Kan, R.W. Dutton

#Hot carriers #MOSFET circuits #Electrons #Impact ionization #Computational modeling #Substrates #High definition video #Integrated circuit modeling #Power engineering and energy #Circuit simulation

"What can computer aided engineering do for the SoC era ?"

International Conference on Simulation of Semiconductor Processes and Devices· ·Trang 211-211·2002

H. Masuda, M. Orlowski, R.W. Dutton, M. Fukuma, S.-W. Lee, W. Schoenmaker, S. Selberherr, T. Wada

#Computer aided engineering #Timing #National electric code #Process design #Electronics industry #Technological innovation

A new SP (simultaneous polishing) model for copper CMP process

International Conference on Simulation of Semiconductor Processes and Devices· ·Trang 257-260

T. Ohta, K. Suzuki

#Copper #Stress #Equations #Accuracy #Testing #Electronic design automation and methodology #Electronic mail #Frequency #Convolution

Tổng số: 69