27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium
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Twenty Seventh Annual IEEE/CPMT/SEMI International Electronics Manufacturing Technology Symposium (Cat. No.02CH37299)
- 2002
Presents the front cover of the proceedings record.
Reliability issues in direct chip attach assemblies using reflow or no-flow underfill
- Trang 73-77
The encapsulation or underfilling of flip chips is critical for the widespread
success of flip-chip-on-board type assemblies. The use of an underfill reduces
the stresses on the solder joints that result from the coefficient of thermal
expansion (CTE) mismatch between the different materials. The mismatch in the
CTE between the chip, solder joint, and the substrate influences the reliability
of th...
#Assembly #Thermal stresses #Flip chip #Soldering #Lead #Materials reliability #Passivation #Encapsulation #Thermal expansion #Joining materials
A structured approach to lead-free IC assembly transitioning
- Trang 215-222
Market forces, trade restrictions, and customer perceptions rather than
environmental realities have driven the lead-free movement. However, it cannot
be turned around. Consequently, manufacturers, suppliers, and industry consortia
have all been working towards a common acceptable drop-in replacement for the
standard eutectic SnPb. Most U.S. and European groups support the use of SnAgCu
alloys for...
#Environmentally friendly manufacturing techniques #Assembly #Semiconductor device manufacture #Semiconductor device packaging #Lead compounds #Manufacturing industries #Soldering #Production #Logistics #Pulp manufacturing
Removable tape using thermoplastic adhesive for QFN assembly process
- Trang 190-192
The miniaturization of IC packages is progressing rapidly with the increasing
demand for mobile electronic equipment. In particular, the demand for the QFN
(quad flat non-leaded package), a lead frame type CSP, is increasing now. The
productivity of the QFN assembly process can become much higher by using the MAP
(molded array packaging) technology. In that technology, QFN support tape is a
key ma...
#Assembly #Packaging machines #Electronic packaging thermal management #Productivity #Integrated circuit packaging #Electronic equipment #Chip scale packaging #Electronics packaging #Resins #Chemicals
A virtual prototyping test bed for electronics assembly
- Trang 130-135
This paper discusses PANDYA, which is a virtual prototyping test bed for
electronics assembly. With the help of virtual reality based environments,
product and process design issues can be studied. PANDYA facilitates
identification of problems by enabling ideas to be proposed, studied, modified
and validated. Such an approach reduces the overall product development time,
reduces overall cost and i...
#Electronic equipment testing #Virtual prototyping #Assembly #Process design #Design engineering #Virtual reality #Product development #Virtual environment #Manufacturing processes #Product design
Ball shear versus ball pull test methods for evaluating interfacial failures in area array packages
- Trang 200-205
In this investigation, a ball pull (tensile) test is investigated as an
alternative to the ball shear test for evaluating the solder joint integrity of
area array packages. The relative effectiveness of the pull and shear methods is
compared using BGA packages with documented susceptibility to brittle
interfacial failure during accelerated temperature cycling tests or isothermal
aging. Accelerated...
#Testing #Packaging #Soldering #Temperature #Accelerated aging #Isothermal processes #Failure analysis #Life estimation #Thermal degradation #Thermal conductivity
Chip scale packaging techniques for RF SAW devices
- Trang 63-66
Wafer-level and chip-scale packaging techniques have been developed for use with
surface acoustic wave (SAW) devices. Both techniques incorporate a process for
bonding a lithium tantalate RF SAW wafer to a mating wafer using adhesive. The
package provides a low loss, hermetic environment for the SAW device resulting
in a product size at least three times smaller than competitively packaged
product...
#Chip scale packaging #Radio frequency #Surface acoustic wave devices #Wafer scale integration #Electronics packaging #Surface acoustic waves #Acoustic waves #Wafer bonding #Lithium compounds #Testing
Pressfit technology for 3-D molded interconnect devices (MID) - A lead-free alternative to solder joints - challenges and solutions concepts
- Trang 238-244
The continuous trend in electronics production towards new substrate materials,
the development of the third dimension by molded interconnect devices (3-D MID)
and the constantly rising integration of functions and miniaturization of
electronic products leads to new challenges for interconnection technology.
Compared to interconnections established by solder materials the pressfit
technology offer...
#Environmentally friendly manufacturing techniques #Lead #Soldering #Connectors #Crystalline materials #Temperature #Continuous production #Thermal stresses #Gases #Cleaning
Finite element analysis of novel substrate design for high performance and cost reduction stacked die CSP
- Trang 267-273
Tessera /spl mu/BGA is the only true CSP package that pass JEDEC level 1
qualification for high performance RAMBUS, DDR and Flash products. The Reduced
Cost Chip Scale Package (RC/sup 2/SP) is currently under development by Meicer
with two plus metal layers thin core rigid board for large panel processing to
reduce cost. Competitive cost, technology and performance are essential to cost
down for /...
#Finite element methods #Performance analysis #Costs #Chip scale packaging #Copper #Qualifications #Springs #Stability #Thermomechanical processes #Etching
Optimizing test strategies during PCB design for boards with limited ICT access
- Trang 364-371
Engineers have used past experience or subjective preference as a means for
assigning test strategies to new products without analyzing the benefits and
weaknesses of various different test approaches in a quantitative manner. DFT
(design for test) software tools that enable testability analysis during board
design allow test engineers to work concurrently with designers. Case study
results demons...
#Design optimization #Software testing #Design for testability #Software design #Production #Costs #Software tools #Design engineering #Software quality #Medical services