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27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium

 

 

 

 

Cơ quản chủ quản:  N/A

Các bài báo tiêu biểu

Solving wire bond process challenges for QFN packaging
- Trang 391-397
E. McDivitt
The introduction of quad flat non-leaded frames now provides manufacturers with an ability to significantly reduce the finished size of a surface mounted component. Component manufacturers have begun to convert many designs to quad flat non-leaded (QFN) format due to the significant cost savings provided. By widening the frame strip and increasing site density, manufacturers can process a larger n... hiện toàn bộ
#Wire #Bonding #Packaging #Costs #Production #Surface finishing #Strips #Manufacturing processes #Assembly #Design optimization
Characteristics of silver-plated film on the second wire bondability
- Trang 382-388
T.Y. Lin, K.L. Davison, W.S. Leong, S. Chua, O. Robin, Y.F. Yao, J.S. Pan, J.W. Chai, K.C. Toh, W.C. Tjiu
Strong bond between the gold wire and the silver-plated leadframe is significantly crucial for maintaining either bondability or reliability during IC (integrated circuit) manufacturing process and IC application in the fields. This study investigated the surface and grain structure of the silver-plated film on the copper leadframe in terms of surface roughness test by atomic force microscopy (AFM... hiện toàn bộ
#Wire #Bonding #Rough surfaces #Surface roughness #Application specific integrated circuits #Atomic force microscopy #Atomic measurements #Force measurement #Transmission electron microscopy #US Department of Energy
Finite element based solder joint fatigue life predictions for a same die size-stacked-chip scale-ball grid array package
- Trang 274-284
B.A. Zahn
Viscoplastic finite-element simulation methodologies were utilized to predict solder joint reliability for a same die size, stacked, chip scale, ball grid array package under accelerated temperature cycling conditions (-40C to +125C, 15 min ramps/15 min dwells). The effects of multiple die attach material configurations were investigated along with the thickness of the mold cap and spacer die. The... hiện toàn bộ
#Finite element methods #Soldering #Fatigue #Acceleration #Temperature #Plastics #Capacitive sensors #Predictive models #Electronics packaging #Chip scale packaging
Decision support for test and debug areas in RF manufacturing
- Trang 136-139
S. Balasubramanian, J. Arbulich, J. Craik, K. Srihari
The last few years have seen the rapid growth of products in the wireless segment. Electronic manufacturing services (EMS) providers have evolved to offer testing and box build services to their customers. Data management is vital in the test, debug and rework areas. Technicians who debug the board provide feedback vital for process and even design improvements. The DebugTech system was developed ... hiện toàn bộ
#Radio frequency #Manufacturing #Spatial databases #System testing #Medical services #Electronic equipment testing #Feedback #Process design #Real time systems #Software debugging
Achieving a world record in ultra high speed wire bonding through novel technology
- Trang 342-347
M. Barp, D. Vischer
The traditional wire bonder design employs a pivoting z-axis, which is mounted on an orthogonal x/y-stage. This type of system is now approaching its physical limitations. The new revolutionary and unique bond head design described in this paper uses entirely new kinematics, which allows for higher accelerations, as well as a stiff, light design. The vibrations, even at highest speed, can be reduc... hiện toàn bộ
#Wire #Bonding #Acceleration #Costs #Permanent magnet motors #Magnetic fields #Flexible manufacturing systems #Semiconductor device manufacture #Flip chip #Standards development
The use of pre-molded leadframe cavity package technologies in photonic and RF applications
- Trang 348-352
A. Longford, B. Radloff
The development of both Opto "photonic" and RF technology into silicon based chip solutions is creating a demand for smaller, more cost effective solutions to house the devices. The suppliers of various cavity package options are now developing new designs to meet the cost and volume production demands generated by these emerging industries. Ceramic based parts are being developed to provide more ... hiện toàn bộ
#Photonics #Radio frequency #Costs #Packaging machines #Plastic packaging #Silicon #Ceramics #Production equipment #Circuits #Lead compounds
Chip-in-polymer: volumetric packaging solution using PCB technology
- Trang 46-49
E. Jung, D. Wojakowski, A. Neumann, C. Landesberger, A. Ostmann, R. Aschenbrenner, H. Reichl
The new challenge is to incorporate not only passive components, but as well active circuitry (ICs) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to <50/spl mu/m total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCBs. Micro via technology allows one to contact the emb... hiện toàn bộ
#Packaging #Thermal management #Silicon #Circuits #Dielectrics #Laminates #Integrated optics #Optical devices #Optical polymers #Contacts
Twenty Seventh Annual IEEE/CPMT/SEMI International Electronics Manufacturing Technology Symposium (Cat. No.02CH37299)
- 2002
Presents the front cover of the proceedings record.
Flux-underfill compatibility and failure mode analysis in high yield flip chip processing
- Trang 78-84
P.N. Houston, D.F. Baldwin, W.M. Tsai
The compatibility of flux and underfill material systems significantly contributes to the formation and growth of process-induced defects and further influences flip chip reliability. Various no-clean fluxes, along with a water-soluble flux used as the baseline, are tested with two fast flow, snap cure underfills. Liquid-to-liquid thermal shock and temperature and humidity tests are conducted to e... hiện toàn bộ
#Failure analysis #Flip chip #Conducting materials #Materials reliability #Thermal conductivity #Electric shock #Temperature #Humidity #Materials testing #System testing
Innovations in defluxing engineered chemistries for removing flux residue on back end solder reflowed bumped wafers
- Trang 67-72
M. Bixenman
The semiconductor industry is in the early stages of a once-in-a-generation packaging substitution. The primary substitution is surface mount packages to area array packages. Within area array packages, a secondary substitution is taking place which is the replacement of wire bonding with flip chip as the die level interface. Flip chip encompasses all bumping technologies that interface a semicond... hiện toàn bộ
#Technological innovation #Chemistry #Semiconductor device packaging #Chemical technology #Cleaning #Flip chip #Electronics industry #Wafer scale integration #Wire #Wafer bonding
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