27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium

The semiconductor industry is in the early stages of a once-in-a-generation packaging substitution. The primary substitution is surface mount packages to area array packages. Within area array packages, a secondary substitution is taking place which is the replacement of wire bonding with flip chip as the die level interface. Flip chip encompasses all bumping technologies that interface a semiconductor die to its next level of interconnect: for example, a BGA substrate, FCIP, DCA and wafer level CSP. Process optimization of the soldering process requires selection of a flux technology, optimized reflow conditions and consideration of the cleaning requirement. Cleaning chemistry selection is driven by the nature of the bumping process used, flux chemistry, reflow condition, number of wafers cleaned per day, and of course environmental, health and safety concerns. Defluxing, which has long been a common practice in the electronic assembly environment, is now more than ever an issue in this emerging technology. This paper presents data on newly developed cleaning chemistries to meet the demanding requirements of wafer level back in processing.

Viscoplastic finite-element simulation methodologies were utilized to predict solder joint reliability for a same die size, stacked, chip scale, ball grid array package under accelerated temperature cycling conditions (-40C to +125C, 15 min ramps/15 min dwells). The effects of multiple die attach material configurations were investigated along with the thickness of the mold cap and spacer die. The solder structures accommodate the bulk of the plastic strain that is generated during accelerated temperature cycling due to the thermal expansion mismatch between the various materials that encompass the stacked die package. Since plastic strain is a dominant parameter that influences low-cycle fatigue, it was used as a basis for evaluation of solder joint structural integrity. The paper discusses the analysis methodologies as implemented in the ANSYS finite element simulation software tool and the corresponding results for the solder joint fatigue life.

The miniaturization of IC packages is progressing rapidly with the increasing demand for mobile electronic equipment. In particular, the demand for the QFN (quad flat non-leaded package), a lead frame type CSP, is increasing now. The productivity of the QFN assembly process can become much higher by using the MAP (molded array packaging) technology. In that technology, QFN support tape is a key material. It needs not only to attach well to the backside of the lead frame to avoid flash burrs in molding, but also to be removed easily from the lead frame and the molding resin with no residue after molding. For this usage, we have developed a new thermoplastic adhesive by optimizing the chemical structure and the characteristics. The new thermoplastic adhesive has a high elastic modulus, low amount of outgassing, and enough adhesive strength at high temperatures. Therefore, our RT series QFN support tape reveals: (1) good wire bondability, (2) no flash burr in molding, and (3) no residue after removal. These tapes contribute more to high yield and high productivity in comparison with the conventional sticky adhesive tape in the QFN assembly process.

Polyimide is typically used as the final layer in silicon technology process integration. Its primary purpose is to protect the topside structures and relieve the interface of stresses introduced during and after encapsulation. However, developments in mold compound technology as well as in wafer fabrication techniques have caused the industry to re-evaluate the need for a polyimide stress buffer. Mold compound fillers have become finer and more spherical, reducing particulate pressure loading from the fillers on the die top surface. Additionally, the use of CMP in wafer fabrication reduces topographical variations, which result in less stress points on the die surface., This paper presents the evaluations that were conducted to assess the continued use of polyimide, and the effort made to eliminate if from some microelectronic packages. Moisture characterization data for several MAPBGA packages are included and package performance without polyimide is assessed. It was concluded that the removal of polyimide from these devices does not significantly affect the yields, but more work needs to be done to realize the limitations.

The introduction of quad flat non-leaded frames now provides manufacturers with an ability to significantly reduce the finished size of a surface mounted component. Component manufacturers have begun to convert many designs to quad flat non-leaded (QFN) format due to the significant cost savings provided. By widening the frame strip and increasing site density, manufacturers can process a larger number of units through the production line and improve assembly efficiency. In addition, each unit occupies a smaller finished volume, reducing the amount of material and providing a cost savings per package. This paper discusses the challenges of wire bond for QFN package designs and describes how new wire bond capabilities and process optimization can improve production yields.

In this investigation, a ball pull (tensile) test is investigated as an alternative to the ball shear test for evaluating the solder joint integrity of area array packages. The relative effectiveness of the pull and shear methods is compared using BGA packages with documented susceptibility to brittle interfacial failure during accelerated temperature cycling tests or isothermal aging. Accelerated temperature cycling is used typically to measure long term solder joint attachment reliability in various use environments and isothermal aging is used to measure susceptibility to degradation following high temperature storage. The shear and pull tests are conducted on packages in the as received condition and after thermal preconditioning. Metallographic failure analysis and scanning electron microscopy with energy dispersive X-ray analyses are used to characterize the solder joints and fracture modes. The ball shear and ball pull results are compared and discussed in terms of the ability to predict susceptibility to interfacial failures in area array packages.

The ultimate way for miniaturization is the usage of flip-chip components. Instead of using costly ceramic PCBs, the use of standard FR-4 substrates offers a wide field for reducing costs. Together with the usage of stencil printing, this leads to a low-cost production chain. By using standard materials and processes, the flip-chips can be integrated in the existing SMT-production line. As the use of environmentally friendly lead-free solder alloys has until now not been tested in detail, the processing and reliability still need to be analyzed. This paper aims to show an overview of the lead-free low-cost flip-chip process chain, starting with a suitable layout of the pads and solder resist openings of the substrate and the openings of the stencil. The influence of the process parameters for solder paste printing is shown. The difficulties of placement of flip-chips are discussed. Possible reflow soldering methods are laid down and the aspects of using nitrogen-atmosphere are also taken into account. Additionally, this paper explains the great importance of the underfill process, points out the possible ways of inspecting flip-chip connections and takes a look at the long-term reliability of flip-chip solder joints. As an outlook a basic approach for selective flip-chip soldering is given.

The traditional wire bonder design employs a pivoting z-axis, which is mounted on an orthogonal x/y-stage. This type of system is now approaching its physical limitations. The new revolutionary and unique bond head design described in this paper uses entirely new kinematics, which allows for higher accelerations, as well as a stiff, light design. The vibrations, even at highest speed, can be reduced to a level that is not conceivable with conventional designs. These equipment capabilities can be used to redefine process-related issues, such as looping, and ball and wedge formation, where low vibrations at high speed are crucial. This new technology achieved a world record in high-speed wire bonding in the lab and leads to a UPH increase of more than 60% with respect to today's conventional best class designs. The benefit of this revolutionary design for the back end manufacturer is the prolonged life expectancy of wire bonding, as the standard interconnect technology. Manufacturers will continue to realize cost savings through productivity improvements and reduce their risk by remaining with a standard that has flourished for decades.

Lead-bonded /spl mu/BGA (/spl mu/BGA/sup /spl reg//) and wire-bonded /spl mu/BGA (/spl mu/BGA/sup /spl reg//-W) packages with flex- and laminate-based substrates have been developed for high-speed memory devices. This work presents the inductance, capacitance, and resistance values for lead-bonded and wire-bonded /spl mu/BGA packages obtained from simulation study to demonstrate and compare their electrical performance. The effect of the bonding technology (lead or wire bond), die-shrink and the type of substrate material on the electrical performance for the /spl mu/BGA package was analyzed by simulation. To verify these results, they were compared to the experimentally measured values. In addition, the electrical performance limitation of the /spl mu/BGA packages was determined by conducting simulation analysis to obtain S-parameters. The bandwidth of the /spl mu/BGA packages was predicted based on the return loss and insertion loss calculated from the S-parameters.

Tessera /spl mu/BGA is the only true CSP package that pass JEDEC level 1 qualification for high performance RAMBUS, DDR and Flash products. The Reduced Cost Chip Scale Package (RC/sup 2/SP) is currently under development by Meicer with two plus metal layers thin core rigid board for large panel processing to reduce cost. Competitive cost, technology and performance are essential to cost down for /spl mu/BGA. Thin core rigid board with hard spring copper instead of TAB tape would also provide better ground shielding and dimensional stability. Thermomechanical reliability study has been performed with design changes of packaging structure. This paper specifically addresses some design characteristics of reduced cost package at sufficient reliability, better thermal and electrical performance with finite element simulation validation. The two metal thin core rigid board with all the layers modeled might suffer thermal compression during copper foil etching process. Hence the need for selecting CTE and Young's modulus of dielectric layer and changing the structure of thin core rigid board to balance the contractility of each side for ensuring the coplanarity is very important.