27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium
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Wafer level underfill - processing and reliability
- Trang 53-62
Underfill materials play a major role in the reliability of flip chip packages. These adhesives have been the subject of much research and development in the last few years, and improvement in material performance has been obtained. However, the assembly method still remains unchanged, with the underfill being dispensed at the individual die level after flip chip reflow. Even with the arrival of "......
#Flip chip #Assembly #Printing #Packaging #Coatings #Curing #Wafer scale integration #Thermal expansion #Chemicals #Semiconductor materials
Pressfit technology for 3-D molded interconnect devices (MID) - A lead-free alternative to solder joints - challenges and solutions concepts
- Trang 238-244
The continuous trend in electronics production towards new substrate materials, the development of the third dimension by molded interconnect devices (3-D MID) and the constantly rising integration of functions and miniaturization of electronic products leads to new challenges for interconnection technology. Compared to interconnections established by solder materials the pressfit technology offer......
#Environmentally friendly manufacturing techniques #Lead #Soldering #Connectors #Crystalline materials #Temperature #Continuous production #Thermal stresses #Gases #Cleaning
Cost and manufacturing optimization of high performance communication hardware using a daughter module
- Trang 115-122
The radical rise in localized component density has forced designers to utilize extremely high density, high layer count printed circuit boards. These high layer counts make the board more difficult, and more expensive to fabricate, resulting in higher costs, reduced raw board yield and a restricted supply base of PCB shops that can build the required substrates. In many instances the need for mul......
#Cost function #Manufacturing #Hardware #Application specific integrated circuits #Printed circuits #Routing #Switches #Silicon #Space technology #Internet
Encapsulation of 1-Up fpBGA from design to production
- Trang 183-189
The plastic near chip scale ball grid array (fpBGA) package has already begun to take over certain segments of the surface mount technology (SMT) industry, and its hold on the market is expected to continue growing over the next few years. A fpBGA in general, offers a smaller footprint than a QFP package with similar pin count. In addition, fpBGA significantly reduces the risk of component handlin......
#Encapsulation #Production #Electronics packaging #Surface-mount technology #Chip scale packaging #Plastic packaging #Electricity supply industry #Plastics industry #Power supplies #Noise reduction
A two-step process for achieving an open test-development environment
- Trang 403-406
For many of today's most advanced ICs and system-on-chip (SoC) devices, test costs have risen to as much as 50% of the total manufacturing cost. A major component of test cost is the time and resources required for test-program development. There are time-proven methods and test-development tools - both in-house and commercial - for translating a semiconductor device's functional events and scan p......
#Costs #Semiconductor device testing #Semiconductor device manufacture #Automatic testing #System-on-a-chip #System testing #Electronic design automation and methodology #Test equipment #Semiconductor devices #Manufacturing industries
A structured approach to lead-free IC assembly transitioning
- Trang 215-222
Market forces, trade restrictions, and customer perceptions rather than environmental realities have driven the lead-free movement. However, it cannot be turned around. Consequently, manufacturers, suppliers, and industry consortia have all been working towards a common acceptable drop-in replacement for the standard eutectic SnPb. Most U.S. and European groups support the use of SnAgCu alloys for......
#Environmentally friendly manufacturing techniques #Assembly #Semiconductor device manufacture #Semiconductor device packaging #Lead compounds #Manufacturing industries #Soldering #Production #Logistics #Pulp manufacturing
Achieving a world record in ultra high speed wire bonding through novel technology
- Trang 342-347
The traditional wire bonder design employs a pivoting z-axis, which is mounted on an orthogonal x/y-stage. This type of system is now approaching its physical limitations. The new revolutionary and unique bond head design described in this paper uses entirely new kinematics, which allows for higher accelerations, as well as a stiff, light design. The vibrations, even at highest speed, can be reduc......
#Wire #Bonding #Acceleration #Costs #Permanent magnet motors #Magnetic fields #Flexible manufacturing systems #Semiconductor device manufacture #Flip chip #Standards development
Ultra-low profile CSPs - new packaging solutions for 300 mm based high-speed, mobile and wireless memory applications
- Trang 173-176
The electronics industry shaped the 90s with exceptional progress in device- and packaging technology. Still the demand continues for lower cost, smaller size and more functionality. The recent deployment of 300 mm wafers, low k dielectrics and copper interconnects are the contribution from the waferfab. The response in the assembly and packaging area are more advanced packages like BGA, CSP, DCA ......
#Packaging machines #Assembly #Substrates #Chip scale packaging #Bonding #Microassembly #Electronics packaging #Process control #Thermal force #Investments
Optimizing wire bonding processes for maximum factory portability
- Trang 329-334
In today's market of finer pitch high-end semiconductor devices, wire bonder set-up time could become too long and expensive without factory specific tools and processes. Reducing set-up time reduces cost and increases efficiency by allowing higher machine utilization. One of the keys to improving machine set-up time is bonder-to-bonder portability. To meet this challenge, wire-bonding equipment i......
#Wire #Bonding processes #Production facilities #Tail #Electronics packaging #Packaging machines #Shape #Electrodes #Milling machines #Semiconductor devices
Ball shear versus ball pull test methods for evaluating interfacial failures in area array packages
- Trang 200-205
In this investigation, a ball pull (tensile) test is investigated as an alternative to the ball shear test for evaluating the solder joint integrity of area array packages. The relative effectiveness of the pull and shear methods is compared using BGA packages with documented susceptibility to brittle interfacial failure during accelerated temperature cycling tests or isothermal aging. Accelerated......
#Testing #Packaging #Soldering #Temperature #Accelerated aging #Isothermal processes #Failure analysis #Life estimation #Thermal degradation #Thermal conductivity