thumbnail

27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium

 

 

 

 

Cơ quản chủ quản:  N/A

Các bài báo tiêu biểu

Effect of flux quantity on Sn-Pb and Pb-free BGA solder shear strength
- Trang 229-237
M. Painaik, D.L. Santos, A.J. McLenaghan, P. Chouta, S.K. Johnson
#Soldering #Testing #Pollution measurement #Vehicles #Electronics packaging #Coordinate measuring machines #Measurement standards #Chip scale packaging #Lead #Pain
Effect of underfill fillet configuration on flip chip package reliability
- Trang 291-303
L. Nguyen, H. Nguyen
#Flip chip #Packaging #Wafer scale integration #Shape #Assembly #Curing #Semiconductor device modeling #Ceramics #Substrates #Acoustic testing
Laser processing - the future of HDI manufacturing
- Trang 149-153
S. Venkat, T. Hannon
#Manufacturing processes #Laser modes #Optical device fabrication #Production #Costs #Packaging #Diodes #Solid lasers #Pulp manufacturing #Electronics industry
Lead-free low-cost flip-chip process chain: layout, process, reliability
- Trang 27-34
P. Woflick, K. Feldmann
#Environmentally friendly manufacturing techniques #Lead #Printing #Ceramics #Costs #Production #Testing #Resists #Reflow soldering #Flip chip solder joints
Finite element analysis of novel substrate design for high performance and cost reduction stacked die CSP
- Trang 267-273
W.R. Yueh, J.C.C. Lee, A.B.L. Wu, J.C.M. Chen
#Finite element methods #Performance analysis #Costs #Chip scale packaging #Copper #Qualifications #Springs #Stability #Thermomechanical processes #Etching
Solder bumping via paste reflow for area array packages
- Trang 1-17
Benlib Huang, Ning-Cheng Lee
#Costs #Throughput #Electronics packaging #Printing #Integrated circuit packaging #Optical arrays #Robustness #Indium #Flip chip #Manufacturing processes
Techno-economic analysis of competing IC packaging protocols
- Trang 426-428
T.A. Hannibal, M. Al Capote
#Integrated circuit packaging #Protocols #Costs #Electronics packaging #Manufacturing #Wafer scale integration #Decision making #Equations #Chip scale packaging #Integrated circuit modeling
Experimental and computational modelling characterisation of fine particle Pb-free solder paste volumes for flip chip assembly applications
- Trang 304-309
G.J. Jackson, M.W. Hendriksen, H. Lu, N.N. Ekere
#Computational modeling #Flip chip #Assembly #Integrated circuit interconnections #Lead #Waste materials #Printed circuits #Manufacturing #Electronic waste #Printing
A study of solder paste release from small stencil apertures of different geometries with constant volumes
- Trang 159-165
S. Aravamudhan, D. Santos, G. Pham-Van-Diep, F. Andres
#Apertures #Geometry #Printing #Assembly #Manufacturing #Flip chip #Chip scale packaging #Electronics packaging #Testing #Printers