Finite element analysis of novel substrate design for high performance and cost reduction stacked die CSP

Tessera /spl mu/BGA is the only true CSP package that pass JEDEC level 1 qualification for high performance RAMBUS, DDR and Flash products. The Reduced Cost Chip Scale Package (RC/sup 2/SP) is currently under development by Meicer with two plus metal layers thin core rigid board for large panel processing to reduce cost. Competitive cost, technology and performance are essential to cost down for /spl mu/BGA. Thin core rigid board with hard spring copper instead of TAB tape would also provide better ground shielding and dimensional stability. Thermomechanical reliability study has been performed with design changes of packaging structure. This paper specifically addresses some design characteristics of reduced cost package at sufficient reliability, better thermal and electrical performance with finite element simulation validation. The two metal thin core rigid board with all the layers modeled might suffer thermal compression during copper foil etching process. Hence the need for selecting CTE and Young's modulus of dielectric layer and changing the structure of thin core rigid board to balance the contractility of each side for ensuring the coplanarity is very important.