27th Annual IEEE/SEMI International Electronics Manufacturing Technology Symposium

Advances in design capabilities and process technologies enable semiconductor manufacturers to create increasingly sophisticated, high-speed integrated circuits with test requirements that seriously challenge traditional test methods and manufacturers' ability to achieve high volume, cost-effective production. To cope with increased test complexity, alternative approaches have largely focused in isolation on design-centric or production-centric tactics, relying in some cases on design-for-test (DFT) methods and in other cases on more powerful automatic test equipment (ATE). Yet approaches to test based solely on such tactics have already fallen behind advances in design and manufacturing, exposing IC manufacturers to the real possibility of creating advanced ICs that cannot be tested within reasonable limits of time or cost. In contrast, a more effective approach targets growing test complexity through a broader strategy that spans product development to facilitate the critical transition from design to production test. At the heart of this strategic approach, test development tools operate within existing design flows, smoothing the traditional barriers between design and test. As a result, logic designers are able to build more testable ICs, and test engineers are able to write more effective test programs. This paper discusses the challenges limiting traditional test methods; describes the requirements for more effective solutions based on a comprehensive design-to-test strategy; and discusses critical technologies needed to deploy effective design-to-test methods required to manage emerging test requirements.

Wire bonding remains the lowest cost and most flexible method for interconnection of semiconductors. A major factor limiting the density of this widely used interconnect technology is wire sweep during the molding processes. Design rules for wire length, wire diameter and bond pad pitch are in many cases constrained by the need to avoid sweep, potentially compromising manufacturers' ability to keep pace with industry roadmaps. For gold wire diameters of 25-30 /spl mu/m, the wire stiffness allows the molding process some latitude. As wire diameters shrink to fit the ball bonds on the periphery of smaller or more complex devices, the molding process has difficulty avoiding wire sweep. The wire encapsulation process described in this paper reduces sweep by as much as an order of magnitude for conventional as well as alternative designs, such as 3D packaging. This paper presents a process that protects the wires in such a way that wire sweep is not a constraint so that assemblers can continue to extend the capabilities of wire bonding. Two process methods are discussed, a batch method and an integrated wirebonder dispense and cure method. The reliability performance of packages made using these processes has been assessed and is reported. The encapsulated test vehicles have achieved JEDEC 3 preconditioning with 3/spl times/ reflow at 240/spl deg/C, temperature cycling and other accelerated life cycle reliability tests. Success at passing JEDEC level 3 and 260/spl deg/ has also been achieved.

Historically, the predominant obstacle to reducing wire bond pitch has been the positional accuracy and repeatability of the force and ultrasonics of the wire-bonding machine. However as the minimum bond pitch moved below 60 /spl mu/m, new barriers have presented themselves. The barriers that are most frequently identified by semiconductor packaging engineers are those associated with probing the die, developing a suitable substrate in which to package it, and molding it without excessive yield loss due to wire sweep. This paper addresses the three key barriers that are enumerated above. It explores performance data and feasibility results from new or improved designs employing standard probing techniques and the feasibility of new ideas. Package substrate solutions-for various market segments are identified, and trade-offs in cost and performance are analyzed. Finally, the paper compares conventional corner gate molding to new molding techniques.

Conventional electronics manufacturing technologies have become unsuitable for high density interconnect structures (HDIS) due to processing limitations, lower manufacturing yields, higher production costs and limited flexibility. Laser processing is one suitable solution for manufacturing HDIS. This is supported by published reports that over 90% of all microvias in HDI PWBs and chip package substrates are formed using laser technology (D.F. Downey et al, 1993). Lasers are ideal primarily due to their high-resolution processing capabilities, fast processing speeds, reliability, versatility and lower cost-of-ownership. Focusing on these factors, this paper highlights key developments in laser processing which are relevant for advancing HDI technology. Particular emphasis is placed on new developments in CO/sub 2/, UV and diode-pumped solid-state laser processing for improved HDI fabrication. Laser performance characteristics, including optimal selection of key process parameters for improved HDI fabrication, and cost-of-ownership models are presented for each laser technology. After discussing the benefits of using existing laser technologies for HDI manufacturing, this paper provides an insight into emerging laser technologies, which are currently under development and driven by the electronics industry. A preview of these technologies and the potential capabilities for the electronics manufacturing industry are presented.

The advantages of leadless devices are many, but along with the new technology come new inspection challenges. This paper explores the post-singulation inspection challenges related to the implementation of leadless packages from the perspective of a user implementing a new packaging technology, as well as that of a supplier of inspection tools working to address unique challenges inherent in the package design. Inspection challenges to be reviewed include coplanarity, pad integrity, board quality, package sides and mark inspection.

The plastic near chip scale ball grid array (fpBGA) package has already begun to take over certain segments of the surface mount technology (SMT) industry, and its hold on the market is expected to continue growing over the next few years. A fpBGA in general, offers a smaller footprint than a QFP package with similar pin count. In addition, fpBGA significantly reduces the risk of component handling damage, reduces power supply noise and offers the same or better performance than leaded packages. With the ever-increasing demand for high density, high I/O count packaging, fpBGA is fast becoming the next generation package. fpBGA package is a method of reducing package size and its pin-to-pin trace gap in order to integrate more functions and reliability in a single space. Conventional encapsulation methodology for fpBGA is by panel molding, normally into multiple (4 or 5) sections. This reduces the substrate material utilization. In this paper design methodology and package reliability for a 1-up (I section) fpBGA will be presented. Reliability consideration includes JEDEC package reliability standard. Package reliability data will be discussed. Package co-planarity data will be compared. The encapsulation results to be discussed will include EMC selection criteria, PMC techniques to control warpage, and the cause of kinked wire and its control methodology.

The paper describes a next-generation solution for land grid array interconnections. The patented cLGA/spl reg/ socket system is a low cost, high volume, conventional material construction product. The product's design and construction make it very stable in response to accelerated life testing, and its low profile yields superior high-speed electrical performance.

The non-flow underfill (NUF) process is an important technology that can be used to reduce the cost of flip chip package assembly. NUF reduces the oxide layer on metal (e.g. bump or pad) and encapsulates the package during bump connection processes such as the reflow process. Generally, in order to achieve higher reliability, filler must be formulated into the underfill material. In the case of NUF, it is difficult to load filler because the filler might become sandwiched between the bump and the substrate, hindering connection. However, we have developed a new NUF system which can connect between bump and substrate according to optimize fine filler distribution and wettability of material, even with much higher filler content formulation. In this paper, we will outline this new filler loaded NUF system, which offers higher connection reliability and thermal cycle reliability.

Polyimide is typically used as the final layer in silicon technology process integration. Its primary purpose is to protect the topside structures and relieve the interface of stresses introduced during and after encapsulation. However, developments in mold compound technology as well as in wafer fabrication techniques have caused the industry to re-evaluate the need for a polyimide stress buffer. Mold compound fillers have become finer and more spherical, reducing particulate pressure loading from the fillers on the die top surface. Additionally, the use of CMP in wafer fabrication reduces topographical variations, which result in less stress points on the die surface., This paper presents the evaluations that were conducted to assess the continued use of polyimide, and the effort made to eliminate if from some microelectronic packages. Moisture characterization data for several MAPBGA packages are included and package performance without polyimide is assessed. It was concluded that the removal of polyimide from these devices does not significantly affect the yields, but more work needs to be done to realize the limitations.

Lead-bonded /spl mu/BGA (/spl mu/BGA/sup /spl reg//) and wire-bonded /spl mu/BGA (/spl mu/BGA/sup /spl reg//-W) packages with flex- and laminate-based substrates have been developed for high-speed memory devices. This work presents the inductance, capacitance, and resistance values for lead-bonded and wire-bonded /spl mu/BGA packages obtained from simulation study to demonstrate and compare their electrical performance. The effect of the bonding technology (lead or wire bond), die-shrink and the type of substrate material on the electrical performance for the /spl mu/BGA package was analyzed by simulation. To verify these results, they were compared to the experimentally measured values. In addition, the electrical performance limitation of the /spl mu/BGA packages was determined by conducting simulation analysis to obtain S-parameters. The bandwidth of the /spl mu/BGA packages was predicted based on the return loss and insertion loss calculated from the S-parameters.