A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs
Tài liệu tham khảo
Murmann, 2003, A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification, IEEE J. Solid-State Circ., 38, 2040, 10.1109/JSSC.2003.819167
Keane, 2005, Background interstage gain calibration technique for pipelined ADCs, IEEE Trans. Circ. Syst.-I: Reg. Pap., 52, 32, 10.1109/TCSI.2004.839534
Chiu, 2004, Least-mean square adaptive digital background calibration of pipelined analog-to-digital converters, IEEE Trans. Circ. Syst. I, 51, 38, 10.1109/TCSI.2003.821306
Taherzadeh-Sani, 2010, Area and power optimization of high-order gain calibration in digitally-enhanced pipelined ADCs, IEEE Trans. Very Large Scale Integr. Syst., 18, 652, 10.1109/TVLSI.2009.2014773
Daito, 2006, A 14-bit 20-MS/s pipelined ADC with digital distortion calibration, IEEE J. Solid State Circ., 41, 2417, 10.1109/JSSC.2006.882886
Shu, 2008, A 15-bit linear 20-MS/s pipelined ADC digitally calibrated with signal-dependent dithering, IEEE J. Solid-State Circ., 43, 342, 10.1109/JSSC.2007.914260
Taherzadeh-Sani, 2006, Digital background calibration of capacitor-mismatch errors in pipelined ADCs, IEEE Trans. Circ. Syst. II, 53, 966, 10.1109/TCSII.2006.879097
Li, 2003, Background calibration techniques for multistage pipelined ADCs with digital redundancy, IEEE Trans. Circ. Syst.-II: Analog Digital Signal Process., 50, 531, 10.1109/TCSII.2003.816921
Yeo, 2014, Digital foreground calibration of capacitor mismatch for SAR ADCs, Electron. Lett., 50, 1423, 10.1049/el.2014.1868
Oshima, 2009, 23-mW 50-MS/s 10-bit pipeline A/D converter with nonlinear LMS foreground calibration
Li, 2012, Digital foreground calibration methods for SAR ADCs
Siragusa, 2004, A digitally enhanced 1.8V 15b 40MS/s CMOS pipe-lined ADC, IEEE J. Solid State Circ., 39, 2126, 10.1109/JSSC.2004.836230
Razavi, 1995
Grace, 2004
Panigada, 2009
Intersil Company’s Product, 2013
Esmaili, 2014, A low-power 13-bit 50MS/s recirculating pipeline analog-to-digital converter, J. Circ. Syst. Comput., 23, 1
Hadidi, 1992, Error analysis in pipeline A/D converters and its application, IEEE Trans. Circ. Syst.-II: Analog Digital Signal Process, 39, 506, 10.1109/82.168942
Montazerolghaem, 2017, A single channel split ADC structure for digital background calibration in pipelined ADCs, IEEE Trans. Very Large Scale Integr. Syst., 25, 1563, 10.1109/TVLSI.2016.2641259
Ingino, 1998, A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter, IEEE J. Solid State Circ., 1920, 10.1109/4.735532
Mousazadeh, 2016, A highly linear CMOS buffer based on third harmonic cancellation, Analog Integr. Circuits Signal Process., 86, 207, 10.1007/s10470-015-0653-5
Razavi, 2001