A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs

Murmann, 2003, A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification, IEEE J. Solid-State Circuits, 38, 2040, 10.1109/JSSC.2003.819167 Shu, 2008, A 15-bit linear 20-MS/s pipelined adc digitally calibrated with signal-dependent dithering, IEEE J. Solid-State Circuits, 43, 342, 10.1109/JSSC.2007.914260 H.-.C. Liu, Z.-.M. Lee, J.-.T. Wu, A Digital Background Calibration Technique for Pipelined Analog-to-Digital Converters, in: Proceedings of IEEE International Symposium on Circuits and Systems Dig. Tech. Papers, 2003, pp. I881–I884. L. Ding, S.W. Sin, U. Seng-Pan, R.P. Martins, A Background Amplifier Offset Calibration Technique for High-Resolution Pipelined ADCs, in: Proceedings of the 8th IEEE International NEWCAS Conference, Montreal, pages: 41-44, 2010. Andersen, 2005, A cost-efficient high-speed 12-bit pipeline ADC in 0.18µm digital CMOS, IEEE J. Solid-State Circuits, 40, 1506, 10.1109/JSSC.2005.847519 Panigada, 2006, Digital background correction of harmonic distortion in pipelined ADCs, IEEE Trans. Circuits Syst., 53, 1885, 10.1109/TCSI.2006.880034 Srinivas, 2006, A distortion compensating flash analog-to-digital conversion technique, IEEE J. Solid-State Circuits, 41, 1959, 10.1109/JSSC.2006.880601 Daito, 2006, A 14-bit 20-MS/s pipelined ADC With digital distortion calibration, IEEE J. Solid-State Circuits, 41, 2417, 10.1109/JSSC.2006.882886 Z.-.S. Cheng, J.-.C. Bor, A CMOS Variable Gain Amplifier with DC Offset Calibration Loop for Wireless Communications, in: Proceedings of International Symposium on VLSI Design, Automation and Test, pp:1-4, 2006. G. Shubao, Zh. Xiaoyan, Q. Yulin, An automatic calibration technique for the OPAMP and its former stage output offset, in: Proceedings of the 6th International Conference on ASIC, Shanghai, 2005, pp: 397-400. Yu, 2008, A 1-V 1.25-GS/S 8-Bit self-calibrated flash ADC in 90-nm digital CMOS, IEEE Trans. Circuits Syst. II, 55, 668, 10.1109/TCSII.2008.921596 Choe, 2000, A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming, IEEE J. Solid-State Circuits, 35, 1781, 10.1109/4.890291 S. Kazeminia, Y. Hesamiafshar, Kh. Hadidi, A. Khoei, On Matching Properties of R-2R Ladders in High Performance Digital-to-Analog Converters, in: Proceedings of the 18th Iranian Conference on Electrical Engineering, Iran, pp:1-4, 2010. S. Kazeminia, S. Mahdavi, Kh. Hadidi, Digitally-Assisted Offset Cancellation Technique for Open-Loop Residue-Amplifiers in High-Resolution and High-Speed ADCs, in: Proceedings of the 23rd International Conference on Mixed Design of Integrated Circuits and Systems, MIXDES, Lodz, pages: 197-202. Chiu, 2004, ‘Least-mean square adaptive digital background calibration of pipelined analog-to-digital converters', IEEE Trans. Circuits Syst. I, 51, 38, 10.1109/TCSI.2003.821306 Q. Lei, W. ZhaoHui, B. Li, H. Wu, ‘Digital Background Calibration For Pipelined SAR ADC Based On LMS algorithm’, in: Proceedings of IEEE International Conference of Electron Devices and Solid-State Circuits, Hong Kong, China, 2013. Taherzadeh-Sani, 2006, ‘Digital background calibration of capacitor-mismatch errors in pipelined ADCs', IEEE Trans. Circuits Syst. II, 53, 966, 10.1109/TCSII.2006.879097 Keane, 2005, ‘Background interstage gain calibration technique for pipelined ADCs’, IEEE Trans. Circuits Syst.-I: Regul. Pap., 52, 32, 10.1109/TCSI.2004.839534 Intersil Company’s Product, Dual 14-Bit, 250/200/125MS/s JESD204B High Speed Serial Output ADC, 2013. Behzad, 1995 Grace, 2004 Ragab, 2015, ‘Digital background calibration for pipelined ADCs based on comparator decision time quantization’, IEEE Trans. Circuits Syst. II, 62, 456, 10.1109/TCSII.2014.2387532