ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605)
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Các bài báo tiêu biểu
A fully differential CMOS OTA for continuous-time filter applications
- Trang 42-45
A CMOS operational transconductance amplifier (OTA) operating from single 3.3 V
power supply is desirable for continuous-time filter applications. The developed
OTA has been used in 100 kHz fifth-order, elliptic filter based on RLC ladder
prototype. Input stage of OTA works as degenerated MOS differential pair with
new concept of active MOS resistance. PSPICE (models BSIM3v3) simulations and
measu...
#Filters #Transconductance #Operational amplifiers #Power amplifiers #Power supplies #Prototypes #SPICE #Semiconductor device modeling #Electrical resistance measurement #Semiconductor device measurement
OFDM modem for ATM based point-multipoint systems
- Trang 138-141
In this paper an application of the OFDM modulation to the "last mile" problem
and the main algorithms involved are described. Moreover, the architectures of
the most important blocks (namely modulator and demodulator) are illustrated and
the design methodology is described. The system has been simulated in FPL and
FXP arithmetic and a VHDL description has been automatically generated by using
COS...
#Modems #Time division multiple access #Asynchronous transfer mode #OFDM modulation #Demodulation #Digital modulation #Optical fiber cables #Optical design #Frequency synchronization #Design methodology
Static-induction transistor for very-high-speed ICs
- Trang 404-407
The structure and model of a static-induction transistor (SIT) with Schottky
barrier for very-high-speed ICs have been developed. Simulation analysis results
of IC logic elements based on complementary SITs is provided. The prospects of
VLSI realization based on complementary SITs is discussed.
#Voltage #Schottky barriers #Very large scale integration #Doping #Tunneling #Ballistic transport #Logic #Frequency #Semiconductor process modeling #Temperature dependence
Architecture of a fault tolerant system for real time embedded applications
- Trang 194-197
This paper aims to present a generalized fault tolerant architecture for time
critical embedded systems where microprocessors/microcontrollers are used as
basic processing elements. If such a system fails at any instant of time, a
standby mechanism is required to take over the responsibility of task handling
automatically, without affecting the processing of the tasks. The case of a
digital teleph...
#Fault tolerant systems #Real time systems #Condition monitoring #Logic #Embedded system #Microprocessors #Microcontrollers #Telephony #Redundancy #Synchronization
Uninterruptible power supplies of small power with the improved shape of output voltage
- Trang 110-113
The modern requirements for quality characteristics of voltage, shaped by
uninterruptible power supplies, are not created in devices of small power (tens
and hundreds watt), produced by domestic and foreign manufacturers. The
necessity of a decrease of weight-dimension characteristics for the results in
formation of output voltage in the form of the rectangular pulse differ
considerably from harmo...
#Uninterruptible power systems #Shape #Voltage #Power supplies #Power amplifiers #Inverters #Nonlinear distortion #Manufacturing #Pulse amplifiers #Modems
Fast and accurate level monitoring circuitry for a burst-mode CMOS laser driver
- Trang 94-97
Fast level monitoring circuitry was implemented in an intelligent 155Mb/s
burst-mode laser driver chip suitable for PON applications. The chip can
regulate the launched optical power of an external laser diode to a required
level within 2.6 /spl mu/s, when the laser and its driver are powered up and
connected to the network for the first time. A 3.3 V digital 0.35 /spl mu/m CMOS
process was used f...
#Monitoring #Driver circuits #Passive optical networks #Optical distortion #Optical receivers #Optical transmitters #Power lasers #Optical feedback #Laser noise #Laser modes
Reconfigurable hardware accelerator for a universal Reed Solomon codec
- Trang 158-161
This paper presents a hardware accelerator for a universal Reed Solomon codec
which can be configured to behave as an encoder or decoder for any RS(n, k, t)
code with programmable field dimension m. For this purpose a hardware-software
codesign approach is followed. A general C implementation of the scheduling for
any RS(n, k, t) code which initially configures the accelerator, gives
comparable pe...
#Hardware #Reed-Solomon codes #Codecs #Read-write memory #Random access memory #Digital signal processing #Decoding #Galois fields #Accelerator architectures #Clocks
Quantization of wavelet coefficients
- Trang 202-205
The wavelet coefficients quantization model is suggested in this paper.
Quantization is represented as addition of noise by equal parts in all bands of
the wavelet transform. The linear approximation model of dependence of
quantizing distortion power from a quantizing interval is considered. It is
shown that use of the pointed model allows increased efficiency of picture
coding.
#Quantization #Wavelet coefficients #Frequency #PSNR #Image coding #Wavelet transforms #Interpolation #Discrete transforms #Hydrogen #Low-frequency noise
Analysis and implementation of a multilevel coded modulation scheme
- Trang 170-173
The authors describe a multilevel coded modulation system for STM1 signaling
(155.52 Mbit/s) with 28 MHz channel spacing. The main goal is to reach good
performance while keeping decoding delay and computational complexity as low as
possible. This is obtained by a two-level scheme based on the partition chain
E/sub 8//RE/sub 8//2E/sub 8/. The outer codes are a rate-1/2 16-ary
convolutional code an...
#Modulation coding #Convolutional codes #Maximum likelihood decoding #Lattices #Frequency #Block codes #Channel spacing #Delay #Field programmable gate arrays #Performance analysis
VCO 4.3 GHz tiêu thụ điện năng thấp và độ ồn pha thấp trong công nghệ CMOS 0.35 /spl mu/m tiêu chuẩn Dịch bởi AI
- Trang 358-361 - 2002
Bài báo báo cáo về hiệu suất độ ồn pha tốt của một VCO tích hợp 4.3 GHz, được
triển khai trong quy trình CMOS kỹ thuật số 0.35 /spl mu/m tiêu chuẩn. Độ ồn pha
đo được tại tần số 4.3 GHz là -120 dBc/Hz tại 1 MHz độ lệch. Mức tiêu thụ điện
chỉ là 3.0 mA tại điện áp cấp 1.5 V.
#Độ ồn pha #VCO điều khiển bằng điện áp #Tụ điện #Tần số #Công nghệ CMOS #Hệ số Q #Quy trình CMOS #Cuộn cảm #Mạch tích hợp số CMOS #Tụ điện đổi biên