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2017 International Conference on System Science and Engineering (ICSSE)

  2325-0925

 

 

Cơ quản chủ quản:  N/A

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Các bài báo tiêu biểu

Hybrid control for swing up and balancing pendubot system: An experimental result
- Trang 450-453 - 2017
Tran Vinh Toan, Tran Thu Ha, Tran Vi Do
This paper presents a hybrid control which includes swing-up and balancing control for pendubot system - a two-link under-actuated robot. The parameters of the pendubot system are measured in the actual pendubot system built in the automation lab, University of Technology and Education HCM City. A hybrid controller which drives the system close to the equilibrium manifold and maintains the system stabilization in the upright position will be developed. The proposed control consists of two stages: swing-up control using partial feedback linearization, and balancing control using linear quadratic regulator. Finally, the controller is verified through both simulation and experimental results. The stability of the pendubot system in simulation showed that the proposed hybrid controller works well. However, the control quality in the experimental model still has some limitations.
#Under-actuated system #hybrid control #partial feedback linearization #LQR #pendubot
A dual-mode 1.8 V-output DC-DC buck converter with on-chip capacitor multiplier in 0.18 um CMOS
- Trang 753-756 - 2017
Van-Ha Nguyen, Yongsea Mo, Wonju Song, Sunghyun Ji, Won-Young Jung, Hanjung Song
This paper presents a dual-mode DC-DC buck converter with on-chip multiplier capacitor-based compensation scheme for portable applications. The proposed converter consists of a power stage and an monolithic CCM/CDM controller that operates with a high clock frequency of 1 MHz. A dual modulation technique is utilized to improve the power conversion efficiency over a wide range of load conditions. In order to reduce chip area the controller, external capacitors are replaced with the on-chip multiplier capacitor-based compensation scheme. Additionally, protection blocks such as over voltage protection (OVP), under voltage lock-out (UVLO) and thermal shutdown (TSD) block are also integrated on the chip. The proposed buck converter was designed and implemented using a 0.18 um CMOS process. The measured results of the fabricated circuit showed a peak efficiency of 94.8%, a ripple voltage of 13.29 mV ripple and an 1.8 V output voltage with a supply voltage ranging from 2.7 to 3.3 V.
#DC-DC power converters #System-on-chip #Capacitors #Switching frequency #RNA #Switches