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A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters
Springer Science and Business Media LLC - Tập 34 - Trang 321-335 - 2018
Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace s......
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection
Springer Science and Business Media LLC - Tập 39 - Trang 447-463 - 2023
The fabless nature of integrated circuits manufacturing leaves them vulnerable to modifications by ill-intentioned third party. There arises a necessity for security measures during their manufacturing to protect them from covert modifications known as hardware Trojans. Static analysis of gate-level synthesized integrated circuits can prove helpful in detecting the presence of unwanted circuitry w......
A hierarchical test generation methodology for digital circuits
Springer Science and Business Media LLC - Tập 1 - Trang 103-123 - 1990
A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the speci......
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique
Springer Science and Business Media LLC - - 2008
With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Experimental results......
Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling
Springer Science and Business Media LLC - Tập 30 - Trang 569-580 - 2014
As a consequence of technology scaling and increasing power consumption of modern high performance designs, various techniques, such as clock gating and Dynamic Voltage and Frequency Scaling (DVFS), have been adapted to address power issues. These techniques are important and desirable to address reliability needs as well as economic issues. From a testing point of view, the introduction of power ......
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