Springer Science and Business Media LLC
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SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement
Springer Science and Business Media LLC - Tập 35 - Trang 655-678 - 2019
Silicon debugging of integrated circuits is exacerbated by the lack of golden responses, highly restricted observability and irreproducible nature of bugs. Debug engineers need to develop better methods that can assist in error localization at lower level(netlist) granularity. It is widely accepted that root-cause analysis of electrical bugs is highly difficult which further elongates the time nee......
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion
Springer Science and Business Media LLC - Tập 38 - Trang 339-352 - 2022
This study applies artificial neural networks (ANNs) to increase stuck-at and delay fault coverage of logic built-in self-test (LBIST) through test point insertion (TPI). Increasing TPI quality is essential for modern logic circuits, but the computational requirements of current TPI heuristics scale unfavorably against increasing circuit complexity, and heuristics that evaluate a TPs quality can m......
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique
Springer Science and Business Media LLC - Tập 24 - Trang 57-65 - 2008
Some asynchronous circuit techniques are proposed to provide a new approach to Single Event Effect (SEE) tolerance in synchronous circuits. Two structures, Double Modular Redundancy (DMR) and Temporal Spatial Triple Modular Redundancy with Dual Clock Triggered Register (TSTMR-D), are presented. Three SEE tolerant 8051 cores with DMR, TSTMR-D and traditional Triple Modular Redundancy (TMR) are impl......
Control and Observation Structure for Analog Circuits with Current Test Data
Springer Science and Business Media LLC - Tập 20 Số 1 - Trang 39-44 - 2004
Reactant and Waste Minimization during Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips using Splitting Trees
Springer Science and Business Media LLC - - 2024
Biological assays around “lab-on-a-chip (LoC)” are required in multiple concentration (or dilution) factors, satisfying specific sample concentrations. Unfortunately, most of them suffer from non-locality and are non-protectable, requiring a large footprint and high purchase cost. A digital geometric technique can generate arbitrary gradient profiles for digital microfluidic biochips (DMFBs). A ne......
Editorial—Special issue on partial scan design
Springer Science and Business Media LLC - Tập 7 - Trang 5-6 - 1995
Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects
Springer Science and Business Media LLC - Tập 35 - Trang 191-200 - 2019
In recent years, FinFET-based Static Random Access Memories (SRAMs) have become a viable solution to provide the storage of big data volume in Systems-on-Chip (SoCs) as well as to assure high performance deep-scaled devices. As consequence, FinFET-based SRAMs are an extremely viable solution to guarantee the high-performance requirements of deep-scaled devices. However, FinFET-based SRAMs can also......
An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects
Springer Science and Business Media LLC - Tập 35 - Trang 87-100 - 2019
Circuit reliability due to Bias Temperature Instability, BTI, has become an important concern in scaled-down complex electronic systems. Even more, current silicon technologies are severely affected by the combined impact of BTI-induced device’s aging and Process-induced device’s parameters variations. The conventional worst-case guardbanding to deal with reliable circuit operation is not longer a......
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor
Springer Science and Business Media LLC - Tập 20 Số 1 - Trang 109-122 - 2004
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