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A HW/SW Cross-Layer Approach for Determining Application-Redundant Hardware Faults in Embedded Systems
Springer Science and Business Media LLC - - 2017
An Efficient Wavelet Based Transient Current Test towards Detection of Data Retention Faults in SRAM
Springer Science and Business Media LLC - Tập 35 - Trang 473-483 - 2019
Advancements in integrated circuit technologies, increasing manufacturing complexity and incessant device scaling inflict new challenges in memory testing and demand for new, sophisticated test methods. Much research has been devoted to reducing the test time of Data Retention Fault (DRF) using March tests. Recent advancements in research rely on using transient current based tests for fault detec...... hiện toàn bộ
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries
Springer Science and Business Media LLC - Tập 38 - Trang 589-602 - 2022
Embedded systems and applications have recently emerged as a domain of high interest to the general public in developing countries. Unfortunately, these countries lack the technological infrastructure for the design, testing, and implementation of projects in the domain. This paper presents a Very Simple Programming Kit (VSPK) for Embedded Systems suitable for practical training, project design, a...... hiện toàn bộ
Self-Testing Embedded Borden t-UED Code Checkers for t = 2 k q − 1 with q = 2 m − 1
Springer Science and Business Media LLC - Tập 24 - Trang 509-527 - 2008
Borden codes are optimal nonsystematic t-unidirectional error detecting (t-UED) codes. A possible method to design a Borden code checker is to map the Borden code words to words of an AN arithmetic code and to check the obtained words with an appropriate AN code checker. For t = q − 1 with q = 2
m
− 1 we show how this method can be modified such that the Borden c...... hiện toàn bộ
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures
Springer Science and Business Media LLC - - 2016
This paper presents a method for optimization of board-level scan test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FP...... hiện toàn bộ
The ΣΔ-BIST Method Applied to Analog Filters
Springer Science and Business Media LLC - Tập 19 - Trang 13-20 - 2003
This paper describes the ΣΔ-BIST method, defined as an analog BIST circuit in the context of mixed signal systems. The test procedure is based on the reuse of existing analog circuits configured as sigma-delta modulators in the analog domain. The test procedure reuses most of existing blocks in a mixed signal system, and thus has small area overhead. Test sensitivity is very high, detecting small ...... hiện toàn bộ
Fault Diagnosis of Smart Grid Distribution System by Using Smart Sensors and Symlet Wavelet Function
Springer Science and Business Media LLC - Tập 33 - Trang 329-338 - 2017
In today’s era of smart grid system scenario, the fault diagnosis is of utmost important task. Present distribution networks change drastically due to expansion and inclusion of large number of distributed generation units into power system at distribution level. To face the challenges of modernized girds, conventional fault diagnosis methodologies require drastic change by making use of advanced ...... hiện toàn bộ
Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations
Springer Science and Business Media LLC - - 1997
In this work we investigate the problem of detection and location ofsingle and unlinked multiple k-coupling faults in n × 1 random-access memories (RAMs). This fault model covers allcrosstalks between any k cells in n × 1 RAMs. The problem of memory testing has been reduced to the problem of the generationof (n,k-1)-exhaustive backgrounds. We have obtained practical test lengths, for a memory size...... hiện toàn bộ
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits
Springer Science and Business Media LLC - Tập 13 - Trang 201-212 - 1998
In this paper, we propose a controller resynthesis technique to enhance the testability of register-transfer level (RTL) controller/data path circuits. Our technique exploits the fact that the control signals in an RTL implementation are don't cares under certain states/conditions. We make an effective use of the don't care information in the controller specification to improve the overall testabi...... hiện toàn bộ
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