Springer Science and Business Media LLC

Advancements in integrated circuit technologies, increasing manufacturing complexity and incessant device scaling inflict new challenges in memory testing and demand for new, sophisticated test methods. Much research has been devoted to reducing the test time of Data Retention Fault (DRF) using March tests. Recent advancements in research rely on using transient current based tests for fault detection. As the test length of a transient current test is comparatively small when compared to other test methods, the probability of detection of this kind of fault during a test period is very low especially in the case of small memory arrays. Large variations in peak amplitude of voltage and charge may occur due to process variations which limits the detection capability of such tests. The main contribution of this paper is enhancing the detection of DRFs in SRAM using transient current test amidst process variations. In this paper, we implement an innovative approach to SRAM test - wavelet based transient supply current test with modified March sequence exploiting Read Equivalent Stress (RES) for DRF detection. The proposed technique can be merged with transient current test using Built-in-Current Sensors (BICS) resulting in full coverage of DRF. In comparison with other techniques that solely rely on software implementation for fault detection, the proposed technique significantly reduces hardware and performance penalties. Simulation results confirm that compared to other methods the proposed technique can provide high standards of reliability and efficiency in DRF detection.

Embedded systems and applications have recently emerged as a domain of high interest to the general public in developing countries. Unfortunately, these countries lack the technological infrastructure for the design, testing, and implementation of projects in the domain. This paper presents a Very Simple Programming Kit (VSPK) for Embedded Systems suitable for practical training, project design, and testing in the domain for use in developing countries. The microcontroller-based system makes it easy to test, teach and train in various areas of embedded systems including programming, communication, signal acquisition and processing, remote control, and domotics. A VSPK prototype has been produced and is used for real-time simulation of Embedded applications. This operation involves the VSPK, the PIC programmer, the PC and the application program to be tested progressively and the displays observed on the LCD and LEDs. The debugging process is easily performed and errors are detected and corrected. The main features of VSPK are low production cost, low power consumption, flexible peripheral pin selection, integrated LCD module, and simple hardware and software environment. Unlike similar kits available for educational purposes, VSPK possesses some advantages such as an integrated graphic color LCD, a configurable internal oscillator, numerically controlled oscillators, testing LEDs, testing buttons, and complete access to multiple programming languages. Two experimental and simple tests for validation of VSPK have been carried out, and the results show that VSPK performs satisfactorily.

Borden codes are optimal nonsystematic t-unidirectional error detecting (t-UED) codes. A possible method to design a Borden code checker is to map the Borden code words to words of an AN arithmetic code and to check the obtained words with an appropriate AN code checker. For t = q − 1 with q = 2 m  − 1 we show how this method can be modified such that the Borden code checkers achieve the self-testing property under very weak conditions. It is only required that no checker input line gets a constant signal and that the Borden code words occur in a random order, making the proposed checkers very suitable for use as embedded checkers. Based on these checkers it is then possible to design embedded Borden t-UED code checkers for t = 2 k q − 1 with q = 2 m  − 1.

This paper presents a method for optimization of board-level scan test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra hardware cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant test time reduction in comparison with state-of-the-art Boundary Scan test tecnique.

This paper describes the ΣΔ-BIST method, defined as an analog BIST circuit in the context of mixed signal systems. The test procedure is based on the reuse of existing analog circuits configured as sigma-delta modulators in the analog domain. The test procedure reuses most of existing blocks in a mixed signal system, and thus has small area overhead. Test sensitivity is very high, detecting small component deviations. Moreover, the proposed test technique can be applied to continuous or sampled time circuits, and the test procedure can be developed in the field. The paper explains the method and presents practical results to validate the proposed approach.

In today’s era of smart grid system scenario, the fault diagnosis is of utmost important task. Present distribution networks change drastically due to expansion and inclusion of large number of distributed generation units into power system at distribution level. To face the challenges of modernized girds, conventional fault diagnosis methodologies require drastic change by making use of advanced infrastructure and technologies. This will be helpful to achieve automation in fault diagnosis tasks, improved power quality, reliability, resilience and self healing property of the power system. This paper proposes the use of smart sensors and advanced communication technology that will be available in future smart grids to carry out automated fault diagnosis tasks using signal processing techniques. Methods of using Standard deviation features of fault transient signal and a fault location factors are proposed. Performance of various scaling levels, features and components of fault transient current signals extracted using the latest non conventional Symlet mother wavelet function are evaluated and compared. The attempt is made to select optimal features and components of fault transient currents to improve the performance of present limited types of available fault locators. The tests are taken on standard model of smart grid distribution system but can be applied for fault diagnosis of any other power equipment. Results show adequate accuracy to extend the use of proposed method for real time applications.

In this work we investigate the problem of detection and location ofsingle and unlinked multiple k-coupling faults in n × 1 random-access memories (RAMs). This fault model covers allcrosstalks between any k cells in n × 1 RAMs. The problem of memory testing has been reduced to the problem of the generationof (n,k-1)-exhaustive backgrounds. We have obtained practical test lengths, for a memory size around 1 M, for detecting up to6-couplings by exhaustive tests and up to 9-couplings bynear-exhaustive tests. The best known test algorithms up to nowprovide for the detection of 5-couplings only in a 1 M memory, usingexhaustive tests. Beyond these parameters, test lengths wereimpractical. Furthermore, our method for generation of(n,k-1)-exhaustive backgrounds yields short test lengths givingrise to considerably shorter testing times than the present mostefficient tests for large n and for k greater than 3. Our test lengths are 50% shorter than other methods for the case of detectingup to 5-couplings in a 1 Mbit RAM. The systematic nature of both ourtests enables us to use a built-in self-test (BIST) scheme, for RAMs, with low hardware overhead. For a 1Mbit memory, the BIST areaoverhead for the detection of 5-couplings is less than 1% for SRAMand 6.8% for a DRAM. For the detection of 9-couplings with 99% or higher probability, the BIST area overhead is less than 0.2% forSRAM and 1.5% for DRAM.

In this paper, we propose a controller resynthesis technique to enhance the testability of register-transfer level (RTL) controller/data path circuits. Our technique exploits the fact that the control signals in an RTL implementation are don't cares under certain states/conditions. We make an effective use of the don't care information in the controller specification to improve the overall testability (better fault coverage and shorter test generation time). If the don't care information in the controller specification leaves little scope for respecification, we add control vectors to the controller to enhance the testability. Experimental results with example benchmarks show an average increase in testability of 9% with a 3–4 fold decrease in test generation time for the modified implementation. The area, delay and power overheads incurred for testability are very low. The average area overhead is 0.4%, and the average power overhead is 4.6%. There was no delay overhead due to this technique in most of the cases.