A Built-in Single Event Upsets Detector for Sequential Cells

Amusan OA, Massengill LW, Baze MP, Bhuva BL, Witulski AF, DasGupta S, Sternberg AL, Fleming PR, Heath CC, Alles ML (2007) Directional sensitivity of single event upsets in 90 nm CMOS due to charge sharing. IEEE Trans Nucl Sci 54(6):2584–2589 Atkinson NM, Ahlbin JR, Witulski AF, Gaspard NJ, Timothy Holman W, Bhuva BL, Zhang EX, Chen L, Massengill LW (2011) Effect of transistor density and charge sharing on single-event transients in 90-nm bulk CMOS. IEEE Trans Nucl Sci 58(6):2578–2584 Black JD, Ball DR II, Robinson WH, Fleetwood DM, Schrimpf RD, Reed RA, Black DA, Warren KM, Tipton AD, Dodd PE, Haddad NF, Xapsos MA, Kim HS, Friendlich M (2008) Characterizing SRAM single event upset in terms of single and multiple node charge collection. IEEE Trans Nucl Sci 55(6):2943–2947 Calin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci 43(6):2874–2878 Chen J, Chen S, He Y, Qin J, Liang B, Liu B, Huang P (2013) Novel layout technique for single-event transient mitigation using dummy transistor. IEEE Trans Device Mater Reliab 13(1):177–184 Costenaro E, Alexandrescu D, Belhaddad K, Nicolaidis M (2013) A practical approach to single event transient analysis for highly complex design. J Electron Test 29(3):301–315 Das S, Bull DM, Whatmough PN (2015) Error-resilient design techniques for reliable and dependable computing. IEEE Trans Device Mater Reliab 15(1):24–34 Dixit A, Wood A (2011) The impact of new technology on soft error rates. Proceedings of IEEE Int Reliab Phys Symp (IRPS), pp. 5B.4.1- 5B.4.7 Gadlage MJ, Ahlbin JR, Narasimham B, Bhuva BL, Massengill LW, Reed RA, Schrimpf RD, Vizkelethy G (2010) Scaling trends in SET pulse widths in sub-100 nm bulk CMOS processes. IEEE Trans Nucl Sci 57(6):3336–3341 Gadlage MJ, Eaton PH, Benedetto JM, Turflinger TL (2005) Comparison of heavy ion and proton induced combinatorial and sequential logic error rates in a deep submicron process. IEEE Trans Nucl Sci 52(6):2120–2124 iROC Technologies (2014) TFIT reference manual, software version 4.0 Jahinuzzaman SM, Rennie DJ, Sachdev M (2009) A soft error tolerant 10T SRAM bit-cell with differential read capability. IEEE Trans Nucl Sci 56(6):3768–3773 Knudsen JE, Clark LT (2006) An area and power efficient radiation hardened by design flip-flop. IEEE Trans Nucl Sci 53(6):3392–3399 Lacoe RC (2008) Improving integrated circuit performance through the application of hardness-by-design methodology. IEEE Trans Nucl Sci 55(4):1903–1925 Lee H-HK, Lilja K, Bounasser M, Linscott I, Inan U (2011) Design framework for soft-error-resilient sequential cells. IEEE Trans Nucl Sci 58(6):3026–3032 Lilja K, Bounasser M, Wen S-J, Wong R, Holst J, Gaspard N, Jagannathan S, Loveless D, Bhuva B (2013) Single-event performance and layout optimization of flip-flops in a 28-nm bulk technology. IEEE Trans Nucl Sci 60(4):2782–2788 Mavis DG, Eaton PH (2007) SEU and SET modeling and mitigation in deep submicron technologies. Proceedings of IEEE Int Reliab Phys Symp. (IRPS), pp. 293–305 Morgan KS, McMurtrey DL, Pratt BH, Wirthlin MJ (2007) A comparison of TMR with alternative fault-tolerant design techniques for FPGAs. IEEE Trans Nucl Sci 54(6):2065–2072 Narasimham B, Gambles JW, Shuler RL, Bhuva BL, Massengill LW (2008) Quantifying the effect of guard rings and guard drains in mitigating charge collection and charge spread. IEEE Trans Nucl Sci 55(6):3456–3460 Noh J, Correas V, Lee S, Jeon J, Nofal I, Cerba J, Belhaddad H, Alexandrescu D, Lee YK, Kwon S (2015) Study of neutron soft error rate (SER) sensitivity: investigation of upset mechanisms by comparative simulation of FinFET and planar MOSFET SRAMs. IEEE Trans Nucl Sci 62(4):1642–1649 Robust Chip Inc. Accuro user’s manual version 8.5 Weste NHE, Harris DM (2011) CMOS VLSI design- a circuits and systems perspective, 4th edn. Addison-Wesley, Boston, p 409–411