Journal of VLSI signal processing systems for signal, image and video technology

In this paper we tackle the problem of error propagation that packet losses can cause in commonly used predictive coding environments. Using multiple description coding (MDC) to generate redundant source data, we propose an algorithm for estimating the lost data in a DPCM coded stream. The novelty of our algorithm is that it uses a sequence search to verify the consistency of the estimates with the received data. In addition for the proposed MDC system, we have developed DPCM encoders which use simple quantizers such as uniform threshold quantizers, and do not require any special indexing or transform. The advantage of this encoder is that it gives good results and it can be constructed using standard codecs.

Stack filters belong to the class of non-linear filters and include the well-known median filter, weighted median filters, order statistic filters and weighted order statistic filters. Any stack filter can be implemented by using the parallel threshold decomposition architecture which allows implementing their non-linear processing by means of a collection of identical binary filters (Boolean logic circuits). Although it is conceptually simple and useful to study the filter properties, this architecture is not practical for direct hardware implementation because as many as (M − 1) binary filters are required for a M-valued input signal and M is large in many applications. In this paper we introduce a new parallel architecture for stack filter implementations. The complexity is now proportional to the window width L of the filter, instead of to M. In most applications L is much smaller than M which translates into efficient hardware implementations. The attractive characteristic of ease of design exhibited by the threshold decomposition architecture is kept. In fact, for a given stack filter both in the conventional implementation and in the proposed one, the same binary filter is required. The key concept supporting the new architecture is a modified decomposition scheme which generates L binary signals for a multi-valued input. As an application example, a complex WOS filter is designed and prototyped in an FPGA.

In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architecture, and control processor. Next, we present the detailed design implementation and the various aspects of physical layout of different sub-blocks of MorphoSys. The physical layout was constrained for 100 MHz operation, with low power consumption, and was implemented using 0.35 μm, four metal layer CMOS (3.3 Volts) technology. We provide simulation results for the MorphoSys architecture (based on VHDL model) for some typical data-parallel applications (video compression and automatic target recognition). The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.

This paper describes a scheme for representing heterogeneous array circuits, in particular those which have been optimized by pipelining or by transposition. Equations for correctness-preserving transformations of these parametric representations are presented. The method is illustrated on developing novel pipelined designs for parallel division. It is estimated that, for a field-programmable gate array implementation, the speed of an integer divider can be doubled at the expense of a 50 percent increase in area.

As digital signal processing systems become larger and clock rates increase, the typical design approach using global clock synchronization will become increasingly difficult. The application of asynchronous clock-free designs to high-performance digital signal processing systems is one promising approach to alleviating this problem. To demonstrate this approach for a typical signal processing task, the system architecture and circuit design of a chip set for implementing high-rate adaptive lattice filters using the asynchronous design techniques is presented.

We propose a configurable and scalable architecture targeted for the implementation of advanced wireless communication algorithms based on matrix computations. A design methodology for programming and configuring the processor architecture is developed. The design entry point is the representation of the algorithm in Matlab/Simulink. The Simulink description is parsed and the algorithm’s Dependence Flow Graph is derived, which is scheduled and space–time mapped onto the proposed architecture. The compiler reconfigures the switch boxes of the proposed hierarchical interconnection network in the architecture. An energy consumption model is derived, and design examples are provided that demonstrate the enhanced energy efficiency of the proposed architecture compared to a state of the art programmable VLIW DSP processors.

ASP (Associative String Processor) architecture and support software provide the base technology for the development of versatile, replaceable, and highly compact building-blocks for the simple construction of modular real-time DSP systems, offering step-function improvements in cost-performance, application flexibility, reliability, and ease of maintenance. Based on a fully programmable and fault-tolerant homogeneous computational architecture, emerging from research at Brunel University and being developed by Aspex Microsystems, ASP modules offer cost-effective support of a particularly wide range of DSP applications, by mapping application data structures to a common string representation supporting content-addressing, parallel processing and a reconfigurable inter-processor communication network. Moreover, by exploiting state-of-the-art microelectronics and packaging technologies, the ASP modules achieve processor packing-densities which are more ussually associated with memory components. Indeed, the ASP has been designed to benefit from the inevitable VLSI-to-ULSI-to-WSI technological trend, with a fully integrated simply scalable, and defect/fault-tolerant processor interconnection strategy. The architecture, software, and implementation of ASP modules are discussed, and the paper indicates that the potential of a peak performance of 1 TOPS (i.e., 1E12 operations (e.g., 12-bit adds) per second) with an input-output bandwidth of 3,200 Mbytes/second could be achieved with only 10 ASP modules, within less than a cubic-foot, dissipating 1 KW, and for less than $1M.