Journal of VLSI signal processing systems for signal, image and video technology
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Journal of VLSI signal processing systems for signal, image and video technology - Tập 18 - Trang 7-8 - 1998
Guest Editors' Introduction
Journal of VLSI signal processing systems for signal, image and video technology - - 2000
Consistent Estimation of Erased Data in a DPCM Based Multiple Description Coding System
Journal of VLSI signal processing systems for signal, image and video technology - Tập 34 - Trang 9-28 - 2003
In this paper we tackle the problem of error propagation that packet losses can cause in commonly used predictive coding environments. Using multiple description coding (MDC) to generate redundant source data, we propose an algorithm for estimating the lost data in a DPCM coded stream. The novelty of our algorithm is that it uses a sequence search to verify the consistency of the estimates with th...... hiện toàn bộ
A Practical Parallel Architecture for Stacks Filters
Journal of VLSI signal processing systems for signal, image and video technology - Tập 38 - Trang 91-100 - 2004
Stack filters belong to the class of non-linear filters and include the well-known median filter, weighted median filters, order statistic filters and weighted order statistic filters. Any stack filter can be implemented by using the parallel threshold decomposition architecture which allows implementing their non-linear processing by means of a collection of identical binary filters (Boolean logi...... hiện toàn bộ
Design and Implementation of the MorphoSys Reconfigurable Computing Processor
Journal of VLSI signal processing systems for signal, image and video technology - Tập 24 - Trang 147-164 - 2000
In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architectur...... hiện toàn bộ
Pipelining and transposing heterogeneous array designs
Journal of VLSI signal processing systems for signal, image and video technology - Tập 5 - Trang 7-20 - 1993
This paper describes a scheme for representing heterogeneous array circuits, in particular those which have been optimized by pipelining or by transposition. Equations for correctness-preserving transformations of these parametric representations are presented. The method is illustrated on developing novel pipelined designs for parallel division. It is estimated that, for a field-programmable gate...... hiện toàn bộ
A clock-free chip set for high-sampling rate adaptive filters
Journal of VLSI signal processing systems for signal, image and video technology - Tập 1 - Trang 345-365 - 1990
As digital signal processing systems become larger and clock rates increase, the typical design approach using global clock synchronization will become increasingly difficult. The application of asynchronous clock-free designs to high-performance digital signal processing systems is one promising approach to alleviating this problem. To demonstrate this approach for a typical signal processing tas...... hiện toàn bộ
Designing systolic architectures for complete Euclidean distance transform
Journal of VLSI signal processing systems for signal, image and video technology - Tập 10 - Trang 169-179 - 1995
A Scalable Configurable Architecture for Advanced Wireless Communication Algorithms
Journal of VLSI signal processing systems for signal, image and video technology - Tập 45 - Trang 127-151 - 2006
We propose a configurable and scalable architecture targeted for the implementation of advanced wireless communication algorithms based on matrix computations. A design methodology for programming and configuring the processor architecture is developed. The design entry point is the representation of the algorithm in Matlab/Simulink. The Simulink description is parsed and the algorithm’s Dependenc...... hiện toàn bộ
ASP modules: cost-effective building-blocks for real-time DSP systems
Journal of VLSI signal processing systems for signal, image and video technology - Tập 1 - Trang 69-84 - 1989
ASP (Associative String Processor) architecture and support software provide the base technology for the development of versatile, replaceable, and highly compact building-blocks for the simple construction of modular real-time DSP systems, offering step-function improvements in cost-performance, application flexibility, reliability, and ease of maintenance. Based on a fully programmable and fault...... hiện toàn bộ
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