Circuits, Systems, and Signal Processing

Motivated by the work of Erdogmus and Principe, we use the error (h,φ)-entropy as the supervised adaptation criterion. Several properties of the (h,φ)-entropy criterion and the connections with traditional error criteria are investigated. By a kernel estimate approach, we obtain the nonparametric estimator of the instantaneous (h,φ)-entropy. Then, we develop the general stochastic information gradient algorithm, and derive the approximate upper bound for the step size in the adaptive linear neuron training. Moreover, the (h,φ) pair are optimized to improve the performance of the proposed algorithm. For the finite impulse response identification with white Gaussian input and noise, the exact optimum φ function is derived. Finally, simulation experiments verify the results and demonstrate the noticeable performance improvement that may be achieved by the optimum (h,φ)-entropy criterion.

In this paper, we propose an efficient design of optimum error nonlinearities (OENL) for adaptive filters which minimizes the steady-state excess mean square error and attains the limit mandated by the Cramer–Rao bound (CRB) of the underlying estimation process. Novelty of the work resides in the fact that the proposed improved optimum error nonlinearities (IOENL) design incorporates the effect of CRB which was ignored in the existing literature. To achieve this, we employ two efficient methods to estimate the variance of a priori estimation error. Therefore, the proposed IOENL does not use any assumption on the distribution of input regressor elements and noise sequence. Neither the assumption of independence on the input regressor is made nor any sort of linearization is assumed. Extensive simulations are done to show the efficiency of the proposed algorithm compared to the standard least mean square algorithm and the standard OENL algorithm.

The vector field convolution (VFC) is an effective external force for active contour models. However, it always comes across premature convergence in extracting complex geometries, especially narrow and deep concavity when the initial contour is set outside of the object boundary. In this letter, a biased vector field convolution (BVFC) external force is proposed. In BVFC, an indicator function with respect to the contour and a narrow band are introduced to biasedly utilize the edges gradient information of a concave region. On the other hand, a feature map which better describes the principal curvatures and equally emphasizes both corners and edges is also introduced. Experimental results demonstrate that the BVFC snake improves the performance in extracting object boundary and shows the ability to converge to concavity compared with several state-of-art active contour models.

Field-programmable gate arrays (FPGAs) are one attractive hardware platform for computing the eigenvalue decomposition of low-dimensional symmetric matrices. For this, one popular method is using the parallel Jacobi algorithm based on coordinate rotations digital computer (CORDIC). We here present a novel efficient FPGA architecture for computing the eigenvalue decomposition, whose main idea is from the fact that rotation matrices in Jacobi’s method belong to a category of special sparse matrices. Based on the above characteristic, matrix multiplications in the parallel Jacobi algorithm can be performed by FPGA efficiently. In addition, we provide one solution for Jacobi’s method to decompose the complex Hermitian matrix. Then, our proposed design is compared with state-of-the-arts on one Xilinx XC7V690T FPGA. Due to the high real-time requirement, we finally take the subspace-based direction of arrival (DOA) estimation in wireless communication as an application example.

Đối với hệ thống tự hồi quy điều khiển đa biến với tiếng ồn hồi quy tự nhiên, mô hình nhận dạng tương ứng của nó bao gồm một ma trận tham số và một véc tơ tham số. Bài báo này trình bày thuật toán lặp dựa trên gradient phân cấp (HGI) để ước lượng tương tác ma trận tham số và véc tơ tham số bằng cách sử dụng nguyên tắc nhận dạng phân cấp và phương pháp tìm kiếm gradient. Kết quả mô phỏng cho thấy thuật toán HGI là hiệu quả.

This paper presents a method for emulating floating memcapacitors with piecewise-linear constitutive relations between time-domain integrals of voltage and charge. The emulation is based on multiple-state floating capacitor, implemented via the switched-capacitor technique. The states of internal switches are derived from the memcapacitor memory, which stores the history of the terminal voltage. The procedure is demonstrated on a two-state memcapacitor. Computer simulations are compared with measurements on the manufactured specimen.

This work presents a video compression method based on sparse representation and dictionary learning algorithms. The proposed scheme achieves superb rate-distortion performance and decent subjective quality, compared to modern standards, especially at low bit-rates. Different from similar works, sparse representation is employed here for both intra-frame and block matching inter-frame motion information. Dividing video frames to reference and current frames, motion vectors and motion compensation residuals of current frames are estimated in regard to reference frames. The sparse codes of reference frames and motion compensation residuals are obtained using learned dictionaries, entropy-coded, and stored or sent to the receiver along with the coded motion field. In the receiver, after decoding the sparse codes and motion vectors, the reference frames and residuals are reconstructed employing the same learned dictionary and the current frames are recovered using the reference frames and motion fields. In the proposed scheme, the Iterative Least Square Dictionary Learning Algorithm (ILS-DLA) and K-SVD dictionary building methods are employed in the DCT domain. The compression rate and quality of the method based on the two dictionary learning algorithms are compared to each other and to H.264/AVC and HEVC modern standards. The results based on PSNR and SSIM criteria show that the proposed approach presents superior performance respect to H.264/AVC and even HEVC for higher bit-rates of QCIF video format, and the K-SVD learning algorithm performs slightly better than the ILS-DLA for the purpose.

Digital video technology has been increasingly needed in various fields, such as telecommunications, entertainment, medicine. Therefore, video compression is required. Motion estimation methods help in improving video compression efficiency by effectively removing the temporal redundancy between successive frames. Several block-based motion estimation (BME) algorithms are being suggested to reduce the coding process’s computational complexity. This paper proposes a new rapid hybrid (BME) algorithm established on the primary search point prediction and advance ending search point strategies. It combines rough adaptive search and effective local search. The coarse search introduces a new motion vector (MV) prediction technique that utilizes the macro-blocks (MBs) Spatio-temporal correlations to optimize the traditional adaptive-rood-pattern search algorithm (ARPS) and speeding up the whole process without affecting the accuracy. In the accurate local search, the cross-formed search pattern using a one-step search (OSS) block matching algorithm is employed, to estimate the actual (MV) with less computation time and further speed up the search efficiency. Exhaustive experiments are performed to demonstrate the present algorithm’s performance over the benchmark schemes concerning specific assessment criteria for results, including the peak signal-to-noise ratio (PSNR), computational complexity and computational gain. The results show that the proposed algorithm is efficient and reliable; it can always give better performance over diamond search (DS) and (ARPS). The conducted test shows an increased performance of search speed while preserving the visual quality of the motion-compensated images, and it achieves 59.76–88.03 speed improvement over (DS) and 20.98–72.06 over (ARPS) for different video sequences. Besides, the suggested method (ARP-OSS) provides the best result compared to (DS) and (ARPS) in terms of time complexity for analyzing all the video samples.

Power consumption in VLSI (Very Large Scale Integration) design is becoming a mainstream issue that cannot be neglected. Low power solution for SoC (system-on-chip) flow gives designers a powerful methodology to analyze, estimate, and optimize today’s increasing power concerns. In this paper, a new power macro-modeling technique at architectural level for the digital electronic systems is presented. This technique allows estimating the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics and the macro-model function is used to construct a set of functions that map the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero-delay simulation is performed for register transfer level (RTL) and the power dissipation is predicted by a macro-model function. The most important contribution of the method is that it allows fast power estimation of IP-based design by a simple addition of individual power consumption. This makes the power modeling of SoCs an easy task that permits evaluation of power features at the architectural level. In order to evaluate our model, we have constructed IP-based digital systems using different IP macro-blocks. In experiments with an individual IP macro-block, the average error is 1–2 %, and for an entire IP-based system with interconnects, the error is measured in the range of 9–15 %.