VLSI test through an improved LDA classification algorithm for test cost reduction
Tài liệu tham khảo
Song, 2020, Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs, IEICE Electron. Express, 18, 10.1587/elex.17.20200420
Stratigopoulos, 2018, Adaptive test with test escape estimation for mixed-signal ICs, IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., 37, 2125, 10.1109/TCAD.2017.2783302
Li, 2008, Static detection of redundant test cases: an initial study, 303
Song, 2019, Novel application of deep learning for adaptive testing based on long short-term memory, 1
Arslan, 2011, Adaptive test optimization through real time learning of test effectiveness, 1
Gupta, 2009, Adaptive Online Testing for Efficient Hard Fault Detection, 343
Singh, 1993, On optimizing VLSI testing for product quality using die-yield prediction, vol. 12, 695
Maxwell, 2011, Adaptive testing: dealing with process variability, vol. 28, 41
Grady, 2013, Adaptive Testing-Cost Reduction through Test Pattern Sampling, 1
Xiao, 2016, Novel applications of deep learning hidden features for adaptive testing, 743
Hapke, 2018, Total Critical Area Based Testing, 1
Pan, 2019, Black-box test-coverage analysis and test-cost reduction based on a bayesian network model, 1
R. Pan, Z. Zhang, X. Li, K. Chakrabarty and X. Gu, "Black-box test-cost reduction based on bayesian network models," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (DOI: 10.1109/TCAD.2020.2994257.).
Shintani, 2014, A variability-aware adaptive test flow for test quality improvement, vol. 33, 1056
Song, 2020, Pattern reorder for test cost reduction through improved SVMRANK algorithm, vol. 8, 147965
Sunter, 2002, Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing cost, 446
Zhao, 2005, Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing, IEEE Trans. Comput. Aided Des. Integrated Circ. Syst., 24, 956, 10.1109/TCAD.2005.847893
Yang, 2008, Detection of transistor stuck-open faults in asynchronous inputs of scan cells, 394
Devta-Prasanna, 2010, Multiple Fault Activation Cycle Tests for Transistor Stuck-Open Faults, 1
Xia, 2019, Copper bridge defects with wafer center signature induced by litho rework process, 1
Guo, 2018, Efficient cell-aware defect characterization for multi-bit cells, 7
Shen, 2005, Extraction of feedback information from circuit netlists, 895
Mande, 2007, Response Surface Methodology for statistical characterization of nano CMOS devices and circuits, 297
Wang, 2017, Test cost reduction methodology for InFO wafer-level chip-scale package, vol. 34, 50
Katragadda, 2018, Algorithm Based Adaptive Parametric Testing for Outlier Detection and Test Time Reduction, 142