Ultrathin high-/spl kappa/ gate dielectric technology for germanium MOS applications

60th DRC. Conference Digest Device Research Conference - Trang 191-192
Chi On Chui1, S. Ramanathan2, B.B. Triplett2, P.C. McIntyre2, K.C. Saraswat1
1Department of Electrical Engineering, Stanford University, Stanford, CA, U.S.A.
2Department of Materials Science and Engineering, Stanford University, Stanford, CA, U.S.A.

Tóm tắt

For the first time, we have successfully demonstrated the use of a high-/spl kappa/ gate dielectric material, ZrO/sub 2/, for CMOS applications on a pure germanium substrate. Using a low-temperature formation technique, we achieved excellent C-V characteristics with hysteresis of 1.5 mV and a capacitance-based equivalent SiO/sub 2/ thickness (t/sub ox,eq/) of about 5 /spl Aring/. Additionally, excellent device uniformity and very high device yield were attained.

Từ khóa

#High K dielectric materials #High-K gate dielectrics #Germanium #Hysteresis #Capacitance-voltage characteristics #Dielectric substrates #Capacitance #MOS devices #Surface treatment #Frequency

Tài liệu tham khảo

ramanathan, 2001, APL, 79, 2621 perkins, 2001, APL, 78, 2357 wilk, 2001, JAP, 89, 5243 sedgwick, 1968, LAP, 39, 5066 lee, 2001, APL, 79, 3344
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60th DRC. Conference Digest Device Research Conference

191-192

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