The use of stressed silicon in MOS transistors and CMOS structures
Tóm tắt
Từ khóa
Tài liệu tham khảo
Krasnikov, G.Ya., Konstructivno-tekhnologicheskie osobennosti submikronnykh MOP-transistors (Constructive and Technological Features of Submicron MOS Transistors), Moscow: Tekhnosfera, Part 1 2002, Part 2 2004.
Orlikovskii, A.A., Silicon Transistor Nanoelectronics, Izv. Vyssh. Uchebn. Zaved., Elektronika, 2006, no. 5, pp. 35–44.
Skotnicki, T. and Monfray, S., Materials and MOS Device Architectures for Sub-32 nm CMOS Nodes, Proc. Int. Conf. on Micro- and Nanoelectronics — 2007 (ICMNE-2007), Moscow-Zvenigorod, 2007, p. L1–01.
Gridchin, V.A. and Dragunov, V.P., Fizika mikrosistem (Physics of Microsystems), Part 1, Novosibirsk: NGTU, 2004.
Aleinikov, A.F., Gridchin, V.A., and Tsapenko, M.P., Datchiki (Sensors), Novosibirsk: NGTU, 2003.
Taskin, A.A., Gridchin, V.A., Cherepov, E.I., et al., Pressure Sensors of the Membrane Type for the Investigation of Aerodynamic Flows, Nauka-Proizvodstvu, 2001, no. 12 (50), pp. 26–30.
Baranskii, P.I., Klochkov, V.P., and Potykevich, I.V., Poluprovodnikovaya elektronika. Spravochnik (Semiconductor Electronics. Handbook), Kiev: Naukova Dumka, 1975.
Arghani, R. et al., Abstracts of Papers, Int. Seminar on Strain Engineering in Non-Volatile Memories, April 2006, p. 32.
Hensel, J.C. and Feher, G., Cyclotron Resonance Experiments in Uniaxially Stressed Silicon: Valence Band Inverse Mass Parameters and Deformation Potential, Phys. Rev., 1963, vol. 129, no. 3, pp. 1041–1062.
Manasevit, H.M., Segis, I.S., and Jones, A.B., Electron Mobility Enhancement in Epitaxial Multilayer Si-Si1−x Gex Alloy Films on (100) Si, Appl. Phys. Lett., 1982, vol. 41, no. 5, pp. 464–466.
People, R. et al., Modification Doping in GexSi1−x /Si Strained Layer Heterostructures, Appl. Phys. Lett., 1984, vol. 45, no. 11, pp. 1231–1233.
Rim, K. et al., Abstracts of Papers, VLSI Symp., June 2002, pp. 98–99.
Wang, H.C. et al., Proc. IEDM Tech. Dig., Dec. 2002, pp. 61–64.
Lee, B.H. et al., Proc. IEDM Tech. Dig., Dec. 2003, pp. 946–948.
Rim, K. et al., Fabrication and Mobility Characteristics of Ultra Thin Strained-Si Directly on Insulator (SSDOI) MOSFETs, Proc. IEDM Tech. Dig., Dec. 2003, pp. 49–52.
Semenova, O. et al., Poverkhnost, 1992, issue 9–11.
Ito, S. et al., Mechanical Stress Effect of Etch-Stop Nitride and Its Impact on Deep Submicron Transistor Design, Proc. IEDM Tech. Dig., Dec. 2000.
Yang, Y.S. et al., Proc. IEDM Tech. Dig., Dec. 2004, pp. 1075–1078.
Shimitzu, A. et al., Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement, Proc. IEDM Tech. Dig., Dec. 2003.
Ota, K. et al., Novel Locally Strained Technique for Performance 55 nm CMOS, Proc. IEDM Tech. Dig., Dec. 2002, pp. 27–30.
Chen, C.H. et al., Abstracts of Papers, VLSI Symp., June 2004, pp. 56–57.
Ghani, T. et al., A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistor, Proc. IEDM Tech. Dig., Dec. 2003, pp. 978–980.
Mistry, K. et al., Abstracts of Papers, VLSI Symp., June 2004, pp. 50–51.
Chan, V. et al., Strain for CMOS Performance Improvement, Proc. IEEE 2005 Custom Integrated Circuits Conf., 2005.
Yang, M. et al., High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations, Proc. IEDM Tech. Dig., Dec. 2003, pp. 453–456.
Yang, M. et al., Abstracts of Papers, VLSI Symp., June 2004, pp. 160–161.
Chang, L. et al., CMOS Circuit Performance Enhancement by Surface Orientation Optimization, Trans. Elec. Dev., 2004, vol. 51, pp. 1621–1627.
Washington, L. et al., p-MOSFET with 200% Mobility Enhancement Induced by Multiple Stressors, IEEE Electron Dev. Lett., 2006, vol. 27, no. 6.
Horstmann, M. et al., Integration and Optimization of Embedded-SiGe, Compressive and Tensile Stressed Liner Films, and Stress Memorization in Advanced SOI CMOS Technologies, IEDM Tech. Dig., Dec. 2005, Report 5, Session 10.
Singer, P., No More Technology Nodes in New ITRS, Semic. Intern., Jan. 2006, pp. 13–14.
Peters, L., Roadmapping 2006 to the Post-CMOS Era, Semic. Intern., March 2006, pp. 17–18.
James, D., Strained Silicon to High-k and Metal Gate, Sol. St. Tech., Nov. 2007.