Temperature dependence of DTMOS transistor characteristics

Solid-State Electronics - Tập 48 - Trang 183-187 - 2004
Jae-Ki Lee1, Nag-Jong Choi1, Chong-Gun Yu1, Jean-Pierre Colinge2, Jong-Tae Park1
1Departments of Electronics Engineering, University of Incheon, #177 Dohwa-dong, Nam-ku, Incheon 402-749, South Korea
2Departments of Electrical and Computer Engineering, University of California, Davis, CA 95616, USA

Tài liệu tham khảo

Colinge, 1987, An SOI voltage-controlled bipolar-MOS devices, IEEE Trans. Electron Devices, 34, 845, 10.1109/T-ED.1987.23005 Assaderaghi, 1994, A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation, Tech. Digest IEDM, 809 Douseki, 1997, A 0.5-V MTCMOS/SIMOX logic gate, IEEE J. Solid-State Circuits, 32, 1604, 10.1109/4.634672 Parke, 1993, Bipolar-FET hybrid-mode operation quarter-micrometer SOI MOSFET’s, IEEE Electron Device Lett., 14, 234, 10.1109/55.215178 Yan, 1997, gate-controlled lateral PNP BJT: characteristics, modeling and circuit applications, IEEE Trans. Electron Devices, 44, 118, 10.1109/16.555443 Momiyama, 2000, A 140 GHz ft and 60 GHz fmax DTMOS Integrated with high-performance SOI logic technology, Tech. Digest of IEDM, 451, 10.1109/IEDM.2000.904353 Chang CY, Su JG, Heng-Ming Hsu, Wong SC, Huang TY, Sun YC. Investigation of bulk dynamic threshold-voltage MOSFET with 65 GHz Nomal Mode Ft and 220 GHz Over-Drive Mode Ft for RF applications. In: Symp. On VLSI Technology Digest of Technical Papers 2001. p. 89–90 Yagishita, 2000, Dynamic threshold voltage damascene metal gate (DT-DMG-MOS) with low threshold voltage, high drive current, and uniform electrical characteristics, Tech. Digest IEDM, 663, 10.1109/IEDM.2000.904406 Rofail, 1997, Experimentally-based analytical model of deep-submicron LDD pMOSFET’s in a Bi-MOS hybrid-mode environment, IEEE Trans. Electron Devices, 44, 1473, 10.1109/16.622604 Hung, 1996, Analytical model for the collector current in SOI gated-controlled hybrid transistor, Solid-State Electron., 39, 1816, 10.1016/S0038-1101(96)00118-9 Terauchi M. Threshold voltage fluctuation analysis in dynamic threshold MOSFET based on charge-sharing. In: IEEE International SOI Conference 2001. p. 53–4 Kuo, 2002, Compact threshold-voltage model for short-channel partially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices, IEEE Trans. Electron Devices, 49, 190, 10.1109/16.974770 Jeon, 1991, A temperature-dependent SOI MOSFET model for high-temperature applications (27–300 °C), IEEE Trans. Electron Devices, 38, 2101, 10.1109/16.83736 Lin, 1996, Temperature-dependent Kink effect model for partially-depleted SOI NMOS devices, IEEE Trans. Electron Devices, 46, 118 Puri, 2001, On the temperature dependence of hysteresis effects in floating-body partially depleted SOI CMOS circuits, IEEE J. Solid-State Circuits, 36, 290, 10.1109/4.902770 Groeseneken, 1991, Temperature dependence of threshold voltage in thin-film SOI MOSFET’s, IEEE Electron Device Lett., 11, 329, 10.1109/55.57923 Assaderaghi, 1997, Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI, IEEE Trans. Electron Devices, 44, 414, 10.1109/16.556151 Colinge, 1997 Vu DP, Boden MJ, Henderson WR, Cheong NK, Zavaracky PM, Adams DA. et al. In: Proceeding IEEE SOS/SOI Technology Conference 1989. p. 165–6