Mô phỏng thống kê cho thiết kế quy trình và tối ưu hóa trong sản xuất vi mạch

Cunningham, S.P., Spanos, C.J., and Voros, K., Semiconductor Yield Improvement: Results and Best Practices, IEEE Trans. Semicond. Manuf., 1995, vol. 8, no. 2, pp. 103-109. Nelayev, V.V., Kazitov, M.V., and Nogotov, E.F., 3D Modeling of Implant Annealing, Inzh.-Fiz. Zh. 1998, vol. 71, no. 6, pp. 1075–1080. Nelayev, V.V. and Kazitov, M.V., Comparative Analysis of the Own Simulation of the Many-Dimensional Thermal Annealing of Ion-Implanted Impurities with Results Obtained by Using of TSUPREM, Proc. 21st Int. Convention on Microelectronics, Electronics and Electronic Technologies (Opatja, Croatia, 1998), pp. 7–10. http://icts.hypermart.net, http://avl.iatp.unibel.by Jaworski, Z., Niewczas, M., and Kuzmicz, W., Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation, Proc. 15th IEEE VLSI Test Symposium 1997, pp. 172–176. TSUPREM-IV, Two-Dimensional Process Simulation Program, Version 6.3, Technology Modeling Associates, 1995, p. 2. Maly, W. and Strojwas, Statistical Simulation of the IC Manufacturing Process, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1982, vol. 1, no. 2, pp. 120-131. Nassif, S.R., Strojvas, A.I., and Director, S.W., FABRICS II-A Statistically Based IC Fabrication Process Simulator, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 1984, vol. 4, no. 1, pp. 40–47. Kuzmicz, W., Denisiuk, W., Gempel, J., et al., Coupling a Statistical Process-Device Simulator with a Circuit Layout Extractor for a Realistic Circuit Simulation of VLSI Circuits, Simulation of Semiconductor Devices and Processes, Selberherr, S., Stippel, H., and Strasser, E., Eds., 1993, pp. 37–40. Nelayev, V.V. and Kazitov, M.V., Construction of Approximating Functions for the Multidimensional Statistical Simulation of IC-Manufacturing Processes, in Aktual'nye problemy tverdotel'noi elektroniki i mikroelektroniki (Current Topics in Solid-State Electronics and Microelectronics, Proc. 5th Natl. Conf., Taganrog, 1998), p. 26. Lejman, A. and Pfitzner, A., Modelling of Doping for Statistical Process/Device Simulators in the IC Design Systems, Proc. 3rd Int. Conf. on Mixed Design of Integrated Circuits and Systems, (Lodz, Poland, 1996), pp. 177–182. Chua, L.O. and Yang, L., Cellular Neural Networks Theory, IEEE Trans. Circuits Syst., 1988, vol. 35, no. 10, pp. 1257–1272. Zadeh, L., Fuzzy Sets and Their Application to Pattern Recognition, Classification and Cluster Analysis, Classi-fication and Clustering, Van Ryzik, J., Ed., New York: Academic, 1977, pp. 198–233. Rietman, E.A., Use of Neural Networks in Modeling Semiconductor Manufacturing Processes: An Example for Plasma Etch Modeling, IEEE Trans. Semicond. Manuf. 1993, vol. 6, no. 4, pp. 343–347. Han, S.-S. and May, G.S., Using Neural Network Process Models to Perform PECVD Silicon Dioxide Recipe Synthesis via Genetic Algorithms, IEEE Trans. Semicond. Manuf., 1997, vol. 10, no. 2, pp. 279–287. Nami, Z., Misman, O., Erbil, A., and May, G.S., Semiempirical Neural Network Modeling of Metal-Organic Chemical Vapor Deposition, IEEE Trans. Semicond. Manuf., 1997, vol. 10, no. 2, pp. 288–294. Zuev, Yu.A. and Ivanov, S.K., Pattern-Recognition Approach to Integrated Information Processing in Dynamical Systems, Vopr. Kibern. 1992, vol. 15, no. 1, pp. 86–106. Nelayev, V.V., Kazitov, M.V., Vatlin, S.I., Voronkovskaya, A.M., and Semenkova, A.M., Computer Simulation of Diffusion Processes in Microelectronics Technology, Proc. SPIE-Int. Soc. Opt. Eng., 1998, vol.3687, pp. 342–346. Gaston, G.J. and Walton, A.J., The Integration of Simulation and Response Surface Methodology for the Optimisation of IC Processes, IEEE Trans. Semicond. Manuf., 1994, vol. 7, no. 1, pp. 22–33. Lu, J.-C., Holton, W.C., Fenner, J.S., Williams, S.C., et al., A New Device Design Methodology for Manufacturability, IEEE Trans. Electron Devices 1998, vol. 45, no. 3, pp. 634–642. Barinov, V.V., Bakhmach, O.F., Kalinin, A.V., Krupkina, T.Yu., and Shelykhmanov, D.E., VLSI Manufacturability Improvement Using the Virtual Fab Concept, Mikroelektronika, 1999, vol. 28, no. 4, pp. 283–292. Kouleshoff, A.A. and Nelayev, V.V., New Approach for the Response Surface Methodology, Proc. 4th Int. Workshop on New Approaches to High-Tech: Nondestructive Testing and Computer Simulations in Science and Engineering (S.-Peterburg, 2000), pp. D16–D19. Bates, D.M. and Watls, D.G., Nonlinear Regression Analysis and Its Applications New York: Wiley, 1988. Ratkowsky, A.D., Nonlinear Regression Modeling: A Unified Approach New York: Marcel Dekker, 1983. Kuzmicz, W.B., Malyshev, V.S., Nelayev, V.V., and Stempitsky, V.R., Optimization of the Integrated Circuit Technology, Proc. 4th Int. Workshop on New Approaches to High-Tech: Nondestructive Testing and Computer Simulations in Science and Engineering (S.-Peterburg, 2000), pp. D19–D22. Kazitov, M.V., Kuzmicz, W.B., Nelayev, V.V., and Stempitsky, V.R., Statistical Many-Dimensional Simulation of VLSI Technology Based on Response Surface Methodology, Proc. SPIE-Int. Soc. Opt. Eng., 1999, vol. 4064, pp. 179–183. Antoniadis, D.A., Hansen, S.E., and Dutton, R.W., Suprem II-A Program for IC Process Modeling and Simulation, Stanford Electronics Lab. Tech. Rep. 5019-2, 1978. Ho, C.P., Plummer, J.D., Hansen, S.E., and Dutton, R.W., VLSI Process Modeling-SUPREM III, IEEE Trans. Electron Devices, 1983, vol. 30, no. 7, pp. 1438–1445. http://www.imio.pw.edu.pl/vlsi/imiocad/syprus/index.html.