Stability of false lock states in a class of phase-lock loops

False lock is a practical, often very perplexing, problem in phase-lock loops (PLLs). When false lock occurs, the PLL may appear to be operating nominally; the phase detector output may have a nominal (usually small) average value, and a conventional lock detector may indicate a correct phase lock state. However, a static average frequency error exists in the loop. While stable false lock states are the most troubling from a practical standpoint, unstable false lock states are possible. This paper describes a method for analyzing the false lock problem in a broad class of PLLs. A functional differential equation and its first variation are developed for the PLL. A qualitative description is given for the functional differential equation solution that corresponds to a false lock state. The stability of the false lock state is related to a characteristic exponent of the first variation equation with respect to the false lock solution. An approximation is developed for this characteristic exponent, and this is used to determine the stability of the false lock state. Finally, the theory is applied to a simple example, and numerical results are given.