Solder joint fatigue models: review and applicability to chip scale packages

Microelectronics Reliability - Tập 40 Số 2 - Trang 231-244 - 2000
W.W Lee1, Luu Nguyen1, Guna S Selvaduray2
1National Semiconductor, P.O. Box 58090, Mail Stop 19-100, Santa Clara, CA 95052, USA
2Department of Materials Engineering San Jose State University One Washington Square San Jose, CA 95192 USA

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Tài liệu tham khảo

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