SPL (super push-pull logic) a bipolar novel low-power high-speed logic circuit

Symposium 1989 on VLSI Circuits - 1989
Usami1, Shiozawa1
1Device Development Center, Hitachi and Limited, Ome, Tokyo, Japan

Tóm tắt

In this contribution we would like to present a new bipolar low -power high -speed logic circuit named SPL (Super Push-pull Logic). At a low POY~~ per gate range of lmw/gate, the calculated path propagation delay time of SPL gates loading wire capacitances of 0.57pF/gate is 2.75 times faster than the one of conventional ECL(Emitter Coupled Logic) gates.

Từ khóa

#Logic gates #Capacitance #Delays #Transistors #Loading #Wires #Large scale integration

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Symposium 1989 on VLSI Circuits

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