Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture
Proceedings. IEEE Asia-Pacific Conference on ASIC, - Trang 209-212
Tóm tắt
The traditional debug tools for chip tests and software developments need huge investment and plenty of time. These problems can be overcome by an embedded debugger based the JTAG boundary scan architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for testability problems. We designed the RED (reusable embedded debugger) using the JTAG boundary scan architecture. The proposed debugger is applicable for not only chip test but also software debugging. Our debugger has an additional hardware module (EICEM: embedded ICE module) for more critical real-time debugging.
Từ khóa
#Reduced instruction set computing #Computer architecture #Software debugging #Ice #Circuits #Protocols #Software testing #Hardware #Costs #InvestmentsTài liệu tham khảo
10.1145/370155.370252
1990
10.1109/VTEST.1999.766706
daniel aga, 1997, Debug and Test of Microcontroller Based Applications using the Boundary Scan Test lnfrastructure, Student Forum within the IEEE International Symposium on Industrial Electronics
key lee, 1993, Data-staionary controller for 32-bit application-specific RISC, Proceedings of ISCAS’93, 3, 1933
haufe, 2000, Real-Time Debugging of Digital Integrated Circuits, Proc Design Automation and Test in Europe Conference
10.1007/978-1-4757-2142-3
10.1007/978-1-4615-3132-6