Process sensitivity and robustness analysis of via-first dual-damascene process

IEEE Transactions on Semiconductor Manufacturing - Tập 16 Số 2 - Trang 307-313 - 2003
Bing‐Yue Tsui1, Chih-Wei Chen2, Shien-Ming Huang2, Shyue‐Shyh Lin2
1Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
2Industrial Technology Research Institute, Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan

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