Phase locked loops for array processors
ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605) - Trang 281-282
Tóm tắt
In modern computers the processor synchronization problem arises. In array processors the clock skew may be significant. The last may lead to the incorrect working of parallel algorithms. The problem of a clock skew in high-speed systems is so important that modern VLSI chips are often supplied by several phase locked loops, placed on one chip. In this case the phase locked loops can be used for creating a distributed system of generators. Here the discrete phase locked loop is considered.
Từ khóa
#Phased arrays #Phase locked loops #Clocks #Equations #Frequency synchronization #Very large scale integration #Stability #Transfer functions #Sufficient conditions #HardwareTài liệu tham khảo
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