PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol’ indices-based engine

Integration - Tập 58 - Trang 9-21 - 2017
Taher Kourany1, Maged Ghoneima2, Emad Hegazi3, Yehea Ismail1
1Center of Nano Electronics and Devices, American University in Cairo/Zewail City of Science and Technology, Cairo, Egypt
2Mechatronics Department, Ain-Shams University, Cairo, Egypt
3Integrated Circuits Lab, Ain-Shams University, Cairo, Egypt

Tài liệu tham khảo

Degrauwe, 1987, IDAC: an interactive design too1 for analog CMOS circuits, IEEE J. Solid-State Circuits, 22, 1106, 10.1109/JSSC.1987.1052861

Harjani, 1989, OASYS: a framework for analog circuit synthesis, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 8, 1247, 10.1109/43.44506

Koh, 1990, OPASYN: a compiler for CMOS operational amplifiers, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9, 113, 10.1109/43.46777

S.K. Gupta, M.M. Hasan, KANSYS: a CAD tool for analog circuit synthesis, in: Proceedings of the Ninth International Conference on VLSI Design, 1996, pp. 333 – 334.

N. Fujip, Second order sensitivity analysis for a class of shape optimization problems, in IEEE 20th International Conference on Industrial Electronics, Control and Instrumentation, Sep. 1994, pp. 1176–1178.

F.M. E1-Turky, R.A. Nordin, BLADES: An expert system for analog circuit design, in Proceedings International Conference Circuits Syst., 1986, pp. 552–555.

H. Yang, A. Agarwal, R. Vemuri, Fast analog circuit synthesis using multi-parameter sensitivity analysis based on element-coefficient diagrams, in Proceedings IEEE Comput. Soc. Annu. Symp. VLSI, Tampa, FL, 2005, pp. 71–76.

H. Yang, R. Vemuri, Efficient Temperature-Dependent Symbolic Sensitivity Analysis and Symbolic Performance Evaluation in Analog Circuit Synthesis, In Proceedings IEEE Design, Automation and Test in Europe, Mar. 2006, pp. 1–2

Giclcn, 2000, Computer-aided Design of Analog and Mixed-Signal Integrated Circuits, Proc. IEEE, 88, 1825, 10.1109/5.899053

C. Toumazou, C.A. Makris, C.M. Berrah, ISAID: A methodology for automated analog IC design, in Proceedings International Symp. Circuits Syst., 1990, vol. 1, pp. 531–555.

E. Berkcan, M. d′Abreu, W. Laughton, Analog compilation based on successive decompositions, in Proceedings Des. Autom. Conference, 1988, pp. 369–375.

Z. Ning, A.J. Mouthaan, H. Wallinga, SEAS: A simulated evolution approach for analog circuit synthesis, in Proceedings Custom Integr. Circuits Conference, 1991, pp. 5.2-1–5.2-4.

K. Swings, S. Donnay, W.M.C. Sansen, HECTOR: A hierarchical topology-construction program for analog circuits based on a declarative approach to circuit modeling, in Proceedings Custom Integr. Circuits Conference, 1991, pp. 5.3/1–5.3/4.

Antao, 1995, ARCHGEN: automated synthesis of analog systems, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 3, 231, 10.1109/92.386223

Horta, 1997, Algorithm-driven synthesis of data conversion architectures, IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst., 10, 1116, 10.1109/43.662675

McConaghy, 2009, Variation aware structural synthesis of analog circuits via hierarchical building blocks and structural homotopy, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28, 1281, 10.1109/TCAD.2009.2023195

Koza, 1992

G.S. Hornby, ALPS: The age-layered population structure for reducing the problem of premature convergence, in: M. Keijzer, M. Cattolico, D. Arnold, V. Babovic, C. Blum, P. Bosman, M.V. Butz, C. CoelloCoello, D. Dasgupta, S.G. Ficici, J. Foster, A. Hernandez-Aguirre, G. Hornby, H. Lipson, P. McMinn, J. Moore, G. Raidl, F. Rothlauf, C. Ryan, D. Thierens (Eds.), Proc. Conf. Genetic Evol. Comput., 2006, vol. 1, pp. 815–822.

R. Martins, N. Lourenço, S. Rodrigues, J. Guilherme, N. Horta, AIDA: Automated Analog IC Design Flow from Circuit Level to Layout, Proceedings of International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Seville, Spain, September 2012

M. Dessouky, M.-M. Louerat, J. Porte, Layout-oriented synthesis of high performance analog circuits, in: Proceedings of Conference on Design, Automation and Test in Europe (DATE), 2000, pp. 53–57.

Habal, 2011, Constraint-based layout-driven sizing of analog circuits, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 30, 1089, 10.1109/TCAD.2011.2158732

H. Yang, R. Vemuri, Efficient symbolic sensitivity based parasitic-inclusive optimization in layout aware analog circuit synthesis, in: Proceedings of the 20th International Conference on VLSI Design, IEEE, 2007, Jan. 2007, 201-206.

L.C. Severo, A. Girardi, Parameter Variation and sensitivity analysis of a two-stage miller amplifier, in: Proceedings IEEE Argentine School of Micro-Nanoelectronics, Tech. and Applications, October 2010, pp. 78–81.

Sobol, 1993, Sensitivity estimates for nonlinear mathematical models, Math. Model. Comput. Exp., 1, 407

Crestaux, 2009, Polynomial chaos expansion for sensitivity analysis, Reliab. Eng. Syst. Saf., 94, 1161, 10.1016/j.ress.2008.10.008

Meng, 2010, Multi-objective optimization design methods based on game theory, 8th World Congr. Intell. Control Autom., 2220

Deb, 2001

Wolfe, 2003, Extraction and use of neural network models in automated synthesis of operational amplifiers, IEEE Trans. CAD, 22, 198, 10.1109/TCAD.2002.806600

Lourenço, 2016, AIDA: layout-aware analog circuit-level sizing with in-loop layout generation, Integr. VLSI J., 10.1016/j.vlsi.2016.04.009

G. Berkol, E. Afacan, G. Dundar, A.E. Pusane, F. Baskaya, A novel yield aware multi-objective analog circuit optimization tool, in: IEEE International Symposium on Circuits and Systems, 2015, pp. 2652–2655.

N. Lourenço, R. Martins, N. Horta, Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction, in: Proceedings of Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1156–1161.

Liu, 2014, GASPAD: a general and efficient mm-wave integrated circuit synthesis method based on surrogate model assisted evolutionary algorithm, IEEE TCAD, 33, 169

Rocha, 2013, A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis, IEEE Congr. Evolut. Comput. (CEC), 2781

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Integration

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9-21

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