New VLSI architectures for three-level correlators

Circuits, Systems, and Signal Processing - Tập 15 - Trang 685-693 - 1996
Rana Ejaz Ahmed1, Saleh A. Alshebeili1
1Department of Electrical Engineering, King Saud University, Riyadh, Saudi Arabia

Tóm tắt

This paper presents the VLSI architectures for three-level correlator design based on 1-μm CMOS technology. The architecture performs very high speed, real-time, three-level cross-correlation of signals. Two architectures, one for serial incoming samples of signals (serial data) and the other for stored signal samples (parallel data), are described in the paper.

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Thông tin
Thông tin xuất bản

Circuits, Systems, and Signal Processing

Tập 15

685-693

Thông tin tác giả