Multi-gate devices for the 32nm technology node and beyond

Hisamoto, 2000, FinFet – a self-aligned double-gate MOSFET scalable to 20nm, IEEE Trans Electron Dev, 47, 2320, 10.1109/16.887014 Kavalieros, 2006, Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering, VLSI Technol Symp, 50 Park, 2001, Pi-gate SOI MOSFET, IEEE Electron Dev Lett, 22, 405, 10.1109/55.936358 von Arnim, 2007, A low-power multi-gate FET CMOS technology with 13.9ps inverter delay large-scale integrated high performance digital circuits and SRAM, VLSI Technol Symp, 106 Pei, 2002, FinFET design considerations based on 3-D simulation and analytical modeling, IEEE Trans Electron Dev, 49, 1411, 10.1109/TED.2002.801263 Van Dal, 2007, Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography, VLSI Technol Symp, 110 Ercken M, Delvaux C, Baerts C, Locorotondo S, Degroote B, Wiaux V, et al. Challenges in patterning 45nm node multiple-gate devices and SRAM cells. In: Proceedings 41st interface symposium. Rooyackers, 2006, Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficienty, IEDM Tech Digest, 993 Lorusso GF et al. Comprehensive approach to MuGFET metrology. In: Metrology, inspection, and process control for microlithography XX, Proc SPIE 6152, 615219, 2006. Collaert, 2005, Tall triple-gate devices with TiN/HfO2 gate stack, VLSI Technol Symp, 108 Singanamalla, 2007, Jpn J Appl Phys, 46, L320, 10.1143/JJAP.46.L320 Witters, 2007, Threshold voltage modulation in FinFET devices through arsenic ion implantation into TiN/HfSiON gate stack, SOI Conference, 31 Ferain, 2007, Metal gate technology using a 3 dielectric cap approach for multiple-VT in NMOS FinFETs, SOI Conference, 141 Dixit, 2005, Analysis of the parasitic source/drain resistance in multiple gate field effect transistors, IEEE Trans Electron Dev, 52, 1132, 10.1109/TED.2005.848098 Hoffmann, 2005, S/D engineering in advanced HfO2/TiN FinFET devices: a view on GIDL (gate-induced drain leakage) and Schottky barriers S/D leakages, IEDM Tech Digest, 743 ITRS Roadmap, Semiconductor Industry Association. CA: San Jose; 2006. Duffy, 2007, Solid phase epitaxy versus random nucleation and growth in sub-20nm wide fin field-effect transistors, Appl Phys Lett, 90, 241912, 10.1063/1.2749186 Lenoble, 2006, Enhanced performance of PMOS MUGFET via integration of conformal plasma-doped source/drain extensions, VLSI Technol Symp, 168 Weize, 2004, Improvement of FinFET electrical characteristics by hydrogen annealing, IEEE Electron Dev Lett, 25, 541, 10.1109/LED.2004.832787 Shin, 2005, Dual stress capping layer enhancement study for hybrid orientation FinFET CMOS technology, IEDM Tech Digest, 1009 Collaert, 2005, Performance improvement of tall triple gate devices with strained SiN layers, IEEE Electron Dev Lett, 26, 820, 10.1109/LED.2005.857692 Nackaerts, 2004, A 0.314μm2 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography, IEDM Tech Digest, 269 Witters, 2005, Integration of tall triple-gate devices with inserted-TaxNy gate in a 0.274μm2 6T-SRAM Cell and advanced CMOS logic circuits, VLSI Technol Symp, 106 Subramanian, 2005, Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs, IEDM Tech Digest, 898 Gustin, 2006, Stochastic matching properties of FinFETs, IEEE Electron Dev Lett, 27, 846, 10.1109/LED.2006.882524