Insights into the operation of negative capacitance FinFET for low power logic applications

Colinge, 2008 Rabaey, 2009 Cheng, 2016, Air spacer for 10 nm FinFET cmos and beyond, 17.1.1 Wang, 2014, Analog building block design in 14 nm FinFET using inversion coefficient, 1 Salahuddin, 2008, Use of negative capacitance to provide voltage amplification for low power nanoscale devices, Nano Lett., 8, 405, 10.1021/nl071804g Khan, 2011, Ferroelectric negative capacitance MOSFET: Capacitance tuning antiferroelectric operation, 11.3.1 Khan, 2014, Negative capacitance in a ferroelectric capacitor, Nature Mater., 14 Khan, 2011, Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures, Appl. Phys. Lett., 99 Awadhiya, 2019, Effect of ferroelectric thickness variation in undoped HfO2-based negative-capacitance field-effect transistor, J. Electron. Mater., 48, 10.1007/s11664-019-07483-1 Yadav, 2021, Design and analysis of improved phase-transition FinFET utilizing negative capacitance, IEEE Trans. Electron Devices, 68, 853, 10.1109/TED.2020.3043222 Liang, 2018, Influence of body effect on sample-and-hold circuit design using negative capacitance fet, IEEE Trans. Electron Devices, 65, 3909, 10.1109/TED.2018.2852679 Bernstein, 2010, Device and architecture outlook for beyond cmos switches, Proc. IEEE, 98, 2169, 10.1109/JPROC.2010.2066530 Pahwa, 2016, Designing energy efficient and hysteresis free negative capacitance FinFET with negative dibl and 3.5x ion using compact modeling approach, 41 Pahwa, 2016, Analysis and compact modeling of negative capacitance transistor with high on-current and negative output differential resistance—part II: Model validation, IEEE Trans. Electron Devices, 63, 4986, 10.1109/TED.2016.2614436 Awadhiya, 2019, Investigating undoped HfO2 as ferroelectric oxide in leaky and non-leaky fe-de heterostructure, Trans. Electr. and Electron. Mater., 1 Liang, 2018, Analysis of dibl effect and negative resistance performance for NCFET based on a compact spice model, IEEE Trans. Electron Devices, 65, 5525, 10.1109/TED.2018.2875661 Liang, 2019, Utilization of negative-capacitance FETs to boost analog circuit performances, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 27, 2855, 10.1109/TVLSI.2019.2932268 Li, 2017, Evaluation of negative capacitance ferroelectric MOSFET for analog circuit applications, IEEE Trans. Electron Devices, 64, 4317, 10.1109/TED.2017.2734279 Lu, 2019, Evaluation of analog circuit performance for ferroelectric soi MOSFETs considering interface trap charges and gate length variations, 1 Liang, 2020, Mismatch of ferroelectric film on negative capacitance FETs performance, IEEE Trans. Electron Devices, 67, 1297, 10.1109/TED.2020.2968050 Aziz, 2016, Physics-based circuit-compatible spice model for ferroelectric transistors, IEEE Electron Device Lett., 37, 805 George, 2016, Device circuit co design of fefet based logic for low voltage processors, 649 George, 2016, Nonvolatile memory design based on ferroelectric FETs, 1 Shukla, 2015, A steep-slope transistor based on abrupt electronic phase transition, Nature Commun., 6, 7812, 10.1038/ncomms8812 Aziz, 2016, Physics-based circuit-compatible spice model for ferroelectric transistors, IEEE Electron Device Lett., 37, 805 Li, 2017, Enabling energy-efficient nonvolatile computing with negative capacitance FET, IEEE Trans. Electron Devices, 64, 3452, 10.1109/TED.2017.2716338 Song, 2005, Landau-Khalatnikov simulations for ferroelectric switching in ferroelectric random access memory application, J. Korean Phys. Soc., 46, 5 Rabe, 2007, 1 Awadhiya, 2018, Passive voltage amplification in non-leaky ferroelectric-dielectric hetero structure, Micro Nano Lett., 13, 10.1049/mnl.2018.5172 Yuan, 2016, Switching-speed limitations of ferroelectric negative-capacitance FETs, IEEE Trans. Electron Devices, 63, 4046, 10.1109/TED.2016.2602209 Li, 2017, Delay and power evaluation of negative capacitance ferroelectric MOSFET based on spice model, IEEE Trans. Electron Devices, 64, 2403, 10.1109/TED.2017.2674020 Li, 2018, Extraction of polarization-dependent damping constant for dynamic evaluation of ferroelectric films and devices, IEEE Electron Device Lett., 39, 1211, 10.1109/LED.2018.2845946 Natarajan, 2014, A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 μm2 sram cell size, 3.7.1 Chauhan, 2015 Li, 2015, Sub-60mv-swing negative-capacitance FinFET without hysteresis, 22.6.1 Pahwa, 2018, Physical insights on negative capacitance transistors in nonhysteresis and hysteresis regimes: MFMIS versus MFIS structures, IEEE Trans. Electron Devices, 65, 867, 10.1109/TED.2018.2794499 2021 Gupta, 2017, Device-circuit analysis of ferroelectric FETs for low-power logic, IEEE Trans. Electron Devices, 64, 3092, 10.1109/TED.2017.2717929 Lin, 2018, Realizing ferroelectric Hf0.5Zr0.5O2 with elemental capping layers, J. Vac. Sci. Technol. B, 36, 10.1116/1.5002558 Awadhiya, 2021, Insight into threshold voltage and drain induced barrier lowering in negative capacitance field effect transistor, Trans. Electr. Electron. Mater., 10.1007/s42341-020-00230-y Li, 2004, Ultrafast polarization switching in thin-film ferroelectrics, Appl. Phys. Lett., 84, 1174, 10.1063/1.1644917 Yuan, 2016, Switching-speed limitations of ferroelectric negative-capacitance FETs, IEEE Trans. Electron Devices, 63, 4046, 10.1109/TED.2016.2602209