Implementation of DVB-RCS turbo decoder for satellite on-board processing
ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605) - Trang 142-145
Tóm tắt
The objective of the present paper is to provide a description of a turbo decoding algorithm for turbo codes standardised for DVB-RCS. It also presents the associated design architecture implemented in very high speed integrated circuit hardware description language (VHDL), as well as synthesis on a specific field programmable gate array (FPGA). The decoding structure was tested using a rapid prototyping system based on high-density Xilinx FPGAs.
Từ khóa
#Digital video broadcasting #Decoding #Satellites #Field programmable gate arrays #Turbo codes #Very high speed integrated circuits #Hardware design languages #Integrated circuit synthesis #Circuit testing #System testingTài liệu tham khảo
10.1002/ett.4460090206
10.1109/11.544563
giancristofaro, 2000, Performances of Novel DVB-RCS Standard Turbo Code and its Use in On-Board Processing Satellites, Proceedings of the EMPS workshop in IEEE EMPS/PIMRC
10.1109/49.661114
bahl, 1974, Optimal decoding of linear codes for minimising symbol error rate, IEEE Trans Inform Theory, it 20, 248
10.1109/ICC.1995.524253
ryan, 0, A Turbo Code Tutorial
2000, Interaction Channel for Satellite Distribution Systems
10.1049/el:20001357
10.1109/ICC.1993.397441